AT83C5135 Atmel Corporation, AT83C5135 Datasheet - Page 10

• Manufacturer Part Number: AT83C5135
• Manufacturer: Atmel Corporation

Specifications of AT83C5135

• Max. Operating Frequency: 32 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 512
• Operating Voltage (vcc): 2.7 to 3.6
• Timers: 4
• Mask Rom (kbytes): 16
• Watchdog: Yes

10
AT83C5134/35/36
Table 4-12.
Signal
Signal
Name
PSEN
Name
AVDD
VREF
AVSS
VDD
RST
VSS
ALE
WR
RD
EA
Type
Type
GND
PWR
GND
PWR
I/O
I/O
I/O
O
O
O
I
Power Signal Description
Description
Read Signal
Read signal asserted during external data memory read operation.
Control input for slave port read access cycles.
Write Signal
Write signal asserted during external data memory write operation.
Control input for slave write access cycles.
Reset
Holding this pin low for 64 oscillator periods while the oscillator is running resets
the device. The Port pins are driven to their reset conditions when a voltage lower
than V
This pin has an internal pull-up resistor which allows the device to be reset by
connecting a capacitor between this pin and VSS.
Asserting RST when the chip is in Idle mode or Power-down mode returns the chip
to normal operation.
This pin is set to 0 for at least 12 oscillator periods when an internal reset occurs
(hardware watchdog or Power monitor).
Address Latch Enable Output
The falling edge of ALE strobes the address into external latch. This signal is
active only when reading or writing external memory using MOVX instructions.
Program Strobe Enable / Hardware conditions Input for ISP
Used as input under reset to detect external hardware conditions of ISP mode
External Access Enable
This pin must be held low to force the device to fetch code from external program
memory starting at address 0000h. It is latched during reset and cannot be
dynamically changed during operation.
Description
Alternate Ground
AVSS is used to supply the on-chip PLL and the USB PAD.
Alternate Supply Voltage
AVDD is used to supply the on-chip PLL and the USB PAD.
Digital Ground
VSS is used to supply the buffer ring and the digital core.
Digital Supply Voltage
VDD is used to supply the buffer ring on all versions of the device.
It is also used to power the on-chip voltage regulator of the Standard versions or
the digital core of the Low Power versions.
USB pull-up Controlled Output
VREF is used to control the USB D+ 1.5 kΩ pull up.
The Vref output is in high impedance when the bit DETACH is set in the USBCON
register.
IL
is applied, whether or not the oscillator is running.
7683C–USB–11/07
Alternate
Alternate
Function
Function
P3.7
P3.6
-
-
-
-
-
-
-
-
-