AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 2

• Manufacturer Part Number: AT89C5131A-L
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-L

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

3. USB - Bad Remote Wake-up Generation
4. UART Interface
5. C51 Core
6. Timer 0/1
7. USB Interface
8. Timer 2 – Baud Rate Generator
2
MOV PCON, #02H; Power down mode activation
NOP
............... ; Put here the first opcode to execute after exiting from power down mode
The remote wake-up generates an SE0 and J state (at the end of the Upstream Resume K) that are reserved by the
Host. When a device is in suspend state and wants to notify an event to the host, it can send an upstream resume in
order to wake up the host. The upstream resume consists of emitting a K state between 1 ms and 15 ms. At the end of
this period, the device should leave the bus in idle state (J state) and wait for a SOF coming before 3ms. But at the end
of the upstream resume, the USB controller drives a SEO (D+ and D- at 0 for 2 bit time) during 100ns before driving the
J state.
Workaround
None.
During UART reception, if the REN bit is cleared between start bit detection and the end of reception, the UART will not
discard the data (RI is set).
Workaround
Test REN bit at the beginning of interrupt routine just after CLR RI, and run the Interrupt routine code only if REN is set.
If CPU is configured in X2 mode when exiting from power down, the first address fetched may be lost
Workaround Two solutions are possible:
a) Set CPU in X1 mode before entering in power-down mode and then restore CPU to X2 mode when the CPU is
woken up.
b) Add a NOP (0x00) opcode just after the instruction which activates the power down mode. As this NOP is randomly
non executed, the behavior of the software is correct.
Example:
If one of the timers 0 and 1 is in X1 mode while the other one is in X2 mode, an unexpected interrupt may randomly
occur for one of the timers.
Workaround
Use the same mode X1 or X2 for both timers. This condition is met if PLL is used to clock the CPU.
Data in Control Endpoint and FIFO may be corrupted if USB macro and CPU write in simultaneously. This condition
occurs if the host cancels a control IN transaction with premature OUT and sends the following SETUP while the C51
is writing into the FIFO instead of the cancellation.
Workaround:
Use 32 bytes FIFO to avoid fragmented data transaction on Control Endpoint.
When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H at the beginning, then UART is not
operational before 10,000 machine cycles.
Workaround
Add the initialization of TH2 and TL2 in the initialization of Timer 2.
AT89C5131A-L Errata
; This NOP is randomly not executed
–
–
Unexpected Interrupt
Power-down Exit Failure in X2 Mode
–
–
Data Corruption in Endpoint0 and FIFO
During Reception, Clearing REN may Generate Unexpected IT
–
Long Start Time
4380F–USB–03/08