AT89C51RD2

Manufacturer Part NumberAT89C51RD2
ManufacturerAtmel Corporation
AT89C51RD2 datasheets
 

Specifications of AT89C51RD2

Flash (kbytes)64 KbytesMax. Operating Frequency60 MHz
Cpu8051-12CMax I/o Pins32
Spi1Uart1
Sram (kbytes)2Self Program MemoryAPI
Operating Voltage (vcc)2.7 to 5.5Timers4
IspUARTWatchdogYes
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Active Errata List
During UART Reception, Clearing REN May Generate Unexpected IT
Timer 2 – Baud Rate Generator – Long Start Time
C51 Core – Bad Exit of Power-down in X2 Mode
PCA
Incorrect Behavior with CPU X2 Mode Bit of HSB
Timer0/1
Extra Interrupt
Boot process - Upper 2Kbytes execution with BLJB=0
Flash/EEPROM - First Read after Load Disturbed
Errata History
Lot Number
All
Errata Descriptions
1. During UART Reception, Clearing REN May Generate Unexpected IT
During UART reception, if the REN bit is cleared between start bit detection and
the end of reception, the UART will not discard the data (RI is set).
Workaround
Test REN at the beginning of Interrupt routine directly after CLR RI, and run the
Interrupt routine code only if REN is set.
2. Timer 2 – Baud Rate Generator
When Timer 2 is used as a baud rate generator, TH2 is not loaded with RCAP2H
at the beginning, then UART is not operational before 10,000 machine cycles.
Workaround
Add the initialization of TH2 and TL2 in the initialization of Timer 2.
3. C51 Core
Bad Exit of Power-down in X2 Mode
When exiting power-down mode by interrupt while CPU is in X2 mode, it leads to
bad execution of the first instruction run when CPU restarts.
Workaround
Set the CPU in X1 mode diretly before entering power-down mode.
4. PCA
Incorrect behavior with CPU X2 mode bit of HSB
When starting the microcontroller in X2 mode upon reset with the X2 fuse bit of
the HSB, the PCA may not work properly when configured with Timer 0 in X1
mode as clock input.
Workaround
Set the CPU in X2 mode by software by writing CKCON register at the begin of
the application.
5. Timer0/1
Extra Interrupt
When Timer0 is in X1 mode and Timer1 in X2 mode and vice versa, extra inter-
rupt may randomly occur for Timer0 or Timer1.
Workaround
Errata List
1, 2, 3, 4, 5, 6, 7
Long Start Time
80C51 MCUs
AT89C51RD2
AT89C51ED2
Errata Sheet
4257E–8051–08/07

AT89C51RD2 Summary of contents

  • Page 1

    ... Extra Interrupt – When Timer0 mode and Timer1 in X2 mode and vice versa, extra inter- rupt may randomly occur for Timer0 or Timer1. Workaround Errata List Long Start Time – 80C51 MCUs AT89C51RD2 AT89C51ED2 Errata Sheet 4257E–8051–08/07 ...

  • Page 2

    ... The ‘Read after load’ issue leads to a wrong Opcode Fetch during the column latch load sequence. Workaround Update of the Flash API Library. A NOP instruction has to be inserted after the load instruction. MOVX @DPTR,A ;Load Column latches NOP ; ADDED INSTRUCTION AT89C51RD2/ED2 2 4257E–8051–08/07 ...

  • Page 3

    ... The PROGRAM DATA BYTE API returns the ‘0xXX’ instead of 0x00 in ACC, but the programmnig operation is sucess- fully completed. 2. API Program Data Page- Incorrect Return Value The PROGRAM DATA PAGE API returns the ‘0xXX’ instead of 0x00 in ACC, but the programmnig operation is sucess- fully completed. AT89C51RD2/ED2 3 Errata List 1,2 4257E–8051–08/07 ...

  • Page 4

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. ©2007 Atmel Corporation. All rights reserved. Atmel tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...