AT89LP213 Atmel Corporation, AT89LP213 Datasheet - Page 18

• Manufacturer Part Number: AT89LP213
• Manufacturer: Atmel Corporation

Specifications of AT89LP213

• Flash (kbytes): 2 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 14
• Spi: 1
• Sram (kbytes): 0.125
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 2
• Isp: SPI/OCD
• Watchdog: Yes

11.2.2
18
AT89LP213/214
Reset Recovery from Power-down
begin. The time-out period is controlled by the Start-up Timer Fuses (see
16). The interrupt pin need not remain low for the entire time-out period.
Figure 11-1. Interrupt Recovery from Power-down (PWDEX = 0)
When PWDEX = “1”, the wake-up period is controlled externally by the interrupt. Again, at the
falling edge on the interrupt pin, power-down is exited and the oscillator is restarted. However,
the internal clock will not propagate until the rising edge of the interrupt pin as shown in
11-2. The interrupt pin should be held low long enough for the selected clock source to stabilize.
After the rising edge on the pin the interrupt service routine will be executed.
Figure 11-2. Interrupt Recovery from Power-down (PWDEX = 1)
The wake-up from Power-down through an external reset is similar to the interrupt with
PWDEX = “0”. At the falling edge of RST, Power-down is exited, the oscillator is restarted, and
an internal timer begins counting as shown in
to propagate to the CPU until after the timer has timed out. The time-out period is controlled by
the Start-up Timer Fuses. (See
a two clock cycle internal reset is generated when the internal clock restarts. Otherwise the
device will remain in reset until RST is brought high.
INTERNAL
INTERNAL
CLOCK
CLOCK
XTAL1
XTAL1
PWD
PWD
INT1
INT1
Table 10-1 on page
Figure
t SUT
16). If RST returns high before the time-out,
11-3. The internal clock will not be allowed
Table 10-1 on page
3538E–MICRO–11/10
Figure