AT90PWM1 Atmel Corporation, AT90PWM1 Datasheet - Page 150

• Manufacturer Part Number: AT90PWM1
• Manufacturer: Atmel Corporation

Specifications of AT90PWM1

• Flash (kbytes): 8 Kbytes
• Pin Count: 24
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 19
• Ext Interrupts: 4
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 0.5
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 105
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 1
• Pwm Channels: 7
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

16.18.1
16.18.2
16.18.3
150
AT90PWM1
Available Input Mode according to Running Mode
Event Capture
Using the Input Capture Unit
Some Input Modes are not consistent with some Running Modes. So the table below gives the
input modes which are valid according to running modes..
Table 40. Available Input Modes according to Running Modes
The PSC can capture the value of time (PSC counter) when a retrigger event or fault event
occurs on PSC inputs. This value can be read by sofware in PICRnH/L register.
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the PICRn Register before the next event occurs, the PICRn will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the PICRn Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Input Mode
Number :
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1 Ramp Mode
Valid
Do not use
Do not use
Valid
Do not use
Do not use
Valid
Valid
Valid
Do not use
Valid
Do not use
2 Ramp Mode
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
4 Ramp Mode
Valid
Valid
Centered Mode
Do not use
Do not use
Do not use
Valid
Do not use
Do not use
Valid
Do not use
Do not use
Do not use
4378C–AVR–09/08