ATmega3290 Atmel Corporation, ATmega3290 Datasheet - Page 153

• Manufacturer Part Number: ATmega3290
• Manufacturer: Atmel Corporation

Specifications of ATmega3290

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11 Register Description
17.11.1
2552K–AVR–04/11
TCCR2A – Timer/Counter Control Register A
For Timer/Counter2, the possible prescaled selections are: clk
clk
Setting the PSR2 bit in GTCCR resets the prescaler. This allows the user to operate with a pre-
dictable prescaler.
• Bit 7 – FOC2A: Force Output Compare A
The FOC2A bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2A is written when
operating in PWM mode. When writing a logical one to the FOC2A bit, an immediate compare
match is forced on the Waveform Generation unit. The OC2A output is changed according to its
COM2A1:0 bits setting. Note that the FOC2A bit is implemented as a strobe. Therefore it is the
value present in the COM2A1:0 bits that determines the effect of the forced compare.
A FOC2A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2A as TOP.
The FOC2A bit is always read as zero.
• Bit 6, 3 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
on page
Table 17-2.
Note:
• Bit 5:4 – COM2A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0
bits are set, the OC2A output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to OC2A pin must be
set in order to enable the output driver.
Bit
(0xB0)
Read/Write
Initial Value
Mode
T2S
0
1
2
3
/128, clk
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
145.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
FOC2A
T2S
Waveform Generation Mode Bit Description
W
7
0
/256, and clk
WGM20
(PWM2)
WGM20
0
1
0
1
R/W
6
0
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
T2S
COM2A1
R/W
5
0
/1024. Additionally, clk
COM2A0
R/W
4
0
ATmega329/3290/649/6490
WGM21
R/W
3
0
TOP
0xFF
0xFF
OCR2A
0xFF
T2S
CS22
R/W
Table 17-2
(1)
2
0
as well as 0 (stop) may be selected.
Update of
OCR2A at
Immediate
TOP
Immediate
BOTTOM
CS21
R/W
1
0
T2S
and
/8, clk
CS20
R/W
“Modes of Operation”
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
T2S
/32, clk
TCCR2A
T2S
/64,
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