ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 209

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

18.10.5
18.10.6
18.11 Examples of Baud Rate Setting
7766F–AVR–11/10
USART Control and Status Register n D– UCSRnD
USART Baud Rate Registers – UBRRLn and UBRRHn
• Bits 7:2 – Reserved bits
These bits are reserved and will be read as ‘0’. Do not set these bits.
• Bits 1 – CTSEN: UART CTS Signal Enable
Set this bit by firmware to enable the transmission flow control signal (CTS). Transmission will
be enabled only if CTS input = 0. Clear this bit to disable the transmission flow control signal.
Transmission will occur without hardware condition. Data Direction Register bit must be correctly
clear to enable the pin as an input.
• Bits 0 – RTSEN: UART RTS Signal Enable
Set this bit by firmware to enable the reception flow control signal (RTS). In this case the RTS
line will automatically rise when the FIFO is full. Clear this bit to disable the reception flow control
signal. Data Direction Register bit must be correctly set to enable the pin as an output.
• Bit 15:12 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, these bit must be
written to zero when UBRRH is written.
• Bit 11:0 – UBRR11:0: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRH contains the four
most significant bits, and the UBRRL contains the eight least significant bits of the USART baud
rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is
changed. Writing UBRRL will trigger an immediate update of the baud rate prescaler.
For standard crystal and resonator frequencies, the most commonly used baud rates for asyn-
chronous operation can be generated by using the UBRR settings in
UBRR values which yield an actual baud rate differing less than 0.5% from the target baud rate,
are bold in the table. Higher error ratings are acceptable, but the Receiver will have less noise
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
7
R/W
0
15
UBRR[7:0]
7
R
R/W
0
0
–
–
6
R/W
0
14
6
R
R/W
0
0
–
–
13
5
R
R/W
0
0
R/W
5
0
–
–
12
4
R
R/W
0
0
R/W
4
0
–
–
11
UBRR[11:8]
3
R/W
R/W
0
0
3
R/W
0
–
10
2
R/W
R/W
0
0
2
R/W
0
–
9
1
R/W
R/W
0
0
1
CTSEN
R/W
0
ATmega16/32U4
Table 18-9
8
0
R/W
R/W
0
0
0
RTSEN
R/W
0
UBRRHn
UBRRLn
to
UCSRnD
Table
18-12.
209