ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 384

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ATmega64

Manufacturer Part Number
ATmega64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Changes from Rev.
2490B-09/02 to
Rev. 2490C-09/02
Changes from Rev.
2490A-10/01 to
Rev. 2490B-09/02
2490Q–AVR–06/10
12. Added information about conversion time for Differential mode with Auto Triggering
13. Added t
14. Updated
1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.
1. Added 64-pad QFN/MLF Package and updated
2. Added the section
3. Added the section
4. Renamed SPMCR to SPMCSR in entire document.
5. Added Some Preliminary Test Limits and Characterization Data
6. Removed Alternative Algortihm for Leaving JTAG Programming Mode.
7. Improved description on how to do a polarity check of the ADC diff results in
8. Updated Programming Figures:
9. Added
10. Updated
11. Updated Description of OSCCAL Calibration Byte.
on
on page
Removed some of the TBD's and corrected data in the following tables and pages:
Table 2 on page
12 on page
on page
327,
See “Leaving Programming Mode” on page 321.
Conversion Result” on page
Figure 138 on page 294
must be connected during Programming mode.
how to program the fuses.
“PROG_PAGEREAD (0x7)” instructions on
More details regarding use of the TWI Power-down operation and using the TWI as master
with low TWBRR values are added into the data sheet. Added the note at the end of the
Rate Generator Unit” on page
on page
In the data sheet, it was not explained how to take advantage of the calibration bytes for 2,
4, and 8 MHz Oscillator selections. This is now added in the following sections:
page
Table 134 on page
WD_FUSE
205.
56,
234.
35.
“Packaging Information” on page
a
“TWI – Two-wire Serial Interface” on page
42,
Table 22 on page
note
Table 14 on page
in
24,
Table 128 on page
“Default Clock Source” on page
“Using all Locations of External Memory Smaller than 64 Kbytes”
regarding
Table 7 on page
330,
and
Figure 147 on page 306
Table 136 on page
204. Added the description at the end of
242.
58,
usage
43,
“DC Characteristics” on page
Table 16 on page
38,
308.
Table 9 on page
of
377.
page
the
Figure 142 on page 301
333, and
“Ordering Information” on page
313.
are updated to also reflect that AVCC
“PROG_PAGELOAD
39.
198.
44,
Table 137
41,
Table 19 on page
Table 10 on page
ATmega64(L)
325,
-
Table
“Address Match Unit”
Table 131 on page
added to illustrate
144.
(0x6)”
52,
41,
Table 20
376.
“ADC
Table
and
384
“Bit

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