ATmega64 Atmel Corporation, ATmega64 Datasheet - Page 56

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ATmega64

Manufacturer Part Number
ATmega64
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Internal Voltage
Reference
Voltage Reference
Enable Signals and
Start-up Time
Watchdog Timer
2490Q–AVR–06/10
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the reset flags to identify a reset condition, the user should read and then reset
the MCUCSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
ATmega64 features an internal bandgap reference. This reference is used for Brown-out Detec-
tion, and it can be used as an input to the Analog Comparator or the ADC. The 2.56V reference
to the ADC is generated from the internal bandgap reference.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
erence is on during the following situations:
1. When the BOD is enabled (by programming the BODEN Fuse).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
Table 20. Internal Voltage Reference Characteristics
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 Mhz. This is
the typical value at V
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in
Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega64 resets and executes from the
Reset Vector. For timing details on the Watchdog Reset, refer to
To prevent unintentional disabling of the Watchdog or unintentional change of Time-out period,
three different safety levels are selected by the fuses M103C and WDTON as shown in Table
21. Safety level 0 corresponds to the setting in ATmega103. There is no restriction on enabling
the WDT in any of the safety levels. Refer to
of the Watchdog Timer” on page 60
Symbol
V
ACBG bit in ACSR).
t
I
BG
BG
BG
Table 22 on page
Parameter
Bandgap reference voltage
Bandgap reference start-up time
Bandgap reference current consumption
CC
Table
= 5V. See characterization data for typical values at other V
58. The WDR – Watchdog Reset – instruction resets the Watchdog
20. To save power, the reference is not always turned on. The ref-
for details.
“Timed Sequences for Changing the Configuration
1.15
Min
page
1.23
Typ
40
10
ATmega64(L)
55.
Max
1.35
70
Units
µA
µs
V
CC
levels. By
56

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