ATmega644P Atmel Corporation, ATmega644P Datasheet
ATmega644P
Specifications of ATmega644P
Available stocks
Related parts for ATmega644P
ATmega644P Summary of contents
Page 1
... Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644PV – Active: 0.4 mA – Power-down Mode: 0.1 µA – Power-save Mode: 0.6 µA (Including 32 kHz RTC) Note: 1. See ”Data Retention” on page ® ® AVR 8-bit Microcontroller ( 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash ATmega164P/V ATmega324P/V ATmega644P/V 8011O–AVR–07/10 ...
Page 2
Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF Figure 1-1. Note: 8011O–AVR–07/10 Pinout ATmega164P/324P/644P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 ...
Page 3
Pinout - DRQFN Figure 1- Table 1- 8011O–AVR–07/10 DRQFN - Pinout ATmega164P Top view B1 B15 B2 B14 B3 B13 B4 B12 ...
Page 4
Overview The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer ...
Page 5
... The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel- opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. 2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P Table 2-1. Device ATmega164P ATmega324P ATmega644P 8011O– ...
Page 6
Pin Descriptions 2.3.1 VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7:PA0) Port A serves as analog inputs to the Analog-to-digital Converter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected ...
Page 7
RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Characteristics” on page 2.3.8 XTAL1 ...
Page 8
About 3.1 Resources A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr. 3.2 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. ...
Page 9
AVR CPU Core 4.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
Page 10
ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three ...
Page 11
Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and ...
Page 12
General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
Page 13
The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
Page 14
... R/W R/W R Initial values respectively for the ATmega164P/324P/644P. Stack Pointer size Device ATmega164P ATmega324P ATmega644P RAMPZ7 RAMPZ6 RAMPZ5 R/W R/W R The Z-pointer used by ELPM and SPM 7 0 RAMPZ directly generated from the selected clock source for the ...
Page 15
Figure 4-5. 1st Instruction Execute 2nd Instruction Execute 3rd Instruction Execute Figure 4-6 operation using two register operands is executed, and the result is stored back to the destina- tion register. Figure 4-6. Register Operands Fetch ALU Operation Execute 4.7 ...
Page 16
The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that ...
Page 17
Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep before any pending ; interrupt(s) C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: ...
Page 18
AVR Memories 5.1 Overview This section describes the different memories in the ATmega164P/324P/644P. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164P/324P/644P features an EEPROM Memory for ...
Page 19
Figure 5-1. 5.3 SRAM Data Memory Figure 5-2 The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O ...
Page 20
The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all these addressing modes. The Register File is described in ter File” ...
Page 21
EEPROM Data Memory The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 ...
Page 22
I/O Memory The I/O space definition of the ATmega164P/324P/644P is shown in page 413. All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data ...
Page 23
Register Description 5.6.1 EEARH and EEARL – The EEPROM Address Register Bit 0x22 (0x42) 0x21 (0x41) Read/Write Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as ...
Page 24
While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming. Table 5-1. EEPM1 • Bit 3 – EERIE: EEPROM ...
Page 25
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is ...
Page 26
The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts will occur during execution of these ...
Page 27
The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
Page 28
GPIOR2 – General Purpose I/O Register 2 Bit 0x2B (0x4B) Read/Write Initial Value 5.6.5 GPIOR1 – General Purpose I/O Register 1 Bit 0x2A (0x4A) Read/Write Initial Value 5.6.6 GPIOR0 – General Purpose I/O Register 0 Bit 0x1E (0x3E) Read/Write ...
Page 29
System Clock and Clock Options 6.1 Clock Systems and their Distribution Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...
Page 30
Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 6.1.4 Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous ...
Page 31
Table 6-2. Typ Time-out (V Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual ...
Page 32
Low Power Crystal Oscillator This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 out- put. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be ...
Page 33
Table 6-4. Oscillator Source / Power Conditions Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 6.4 Full Swing Crystal Oscillator This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the ...
Page 34
Table 6-6. Oscillator Source / Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: 6.5 Low Frequency Crystal Oscillator The Low-frequency Crystal ...
Page 35
The capacitance (Ce +Ci) needed at each TOSC pin can be calculated by using: where: – optional external capacitors as described in Figure 8-2 on page29 – the pin capacitance in table 8-8 on ...
Page 36
Calibrated Internal RC Oscillator By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See 25-4 on page 330 The device ...
Page 37
Internal Oscillator The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre- quency is nominal at 3V and 25°C. This clock may be select as the system clock by ...
Page 38
Table 6-15. Power Conditions BOD enabled Fast rising power Slowly rising power When applying an external clock required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the MCU. A variation in ...
Page 39
The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the ...
Page 40
Register Description 6.12.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...
Page 41
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor ...
Page 42
Power Management and Sleep Modes 7.1 Overview Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the ...
Page 43
BOD Disable When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, the BOD is actively monitoring the power supply voltage during a sleep period. To save power possible to disable the BOD by software for some ...
Page 44
Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power- down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2- wire Serial Interface, and the ...
Page 45
Power Reduction Register The Power Reduction Register(PRR), see vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or ...
Page 46
Watchdog Timer If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the ...
Page 47
Register Description 7.12.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...
Page 48
MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 6 – BODS: BOD Sleep The BODS bit must be written to logic one in order to turn off BOD during sleep, see on page BODSE ...
Page 49
Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be ...
Page 50
System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...
Page 51
Figure 8-1. BODLEVEL [2..0] 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to trigger the ...
Page 52
Figure 8-2. TIME-OUT INTERNAL Figure 8-3. TIME-OUT INTERNAL 8.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is not ...
Page 53
Brown-out Detection ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. ...
Page 54
Internal Voltage Reference ATmega164P/324P/644P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.7.1 Voltage Reference Enable Signals and Start-up Time ...
Page 55
Watchdog Timer 8.8.1 Features • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • Possible Hardware fuse Watchdog always ...
Page 56
In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit. 2. Within the next four ...
Page 57
Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this ...
Page 58
Register Description 8.9.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...
Page 59
WDTCSR – Watchdog Timer Control Register Bit (0x60) Read/Write Initial Value • Bit 7 - WDIF: Watchdog Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for ...
Page 60
Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler and 0 The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run- ning. The different prescaling values and their corresponding time-out periods are shown ...
Page 61
Interrupts 9.1 Overview ...
Page 62
Table 9-1. Vector No Notes: Table 9-2 BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This ...
Page 63
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8 Kbytes and the IVSEL bit ...
Page 64
RESET: ldi 0x1F001 0x1F002 0x1F003 0x1F004 0x1F005 When the BOOTRST Fuse is programmed, the Boot section size set to 8 Kbytes and the IVSEL bit in the MCUCR Register is set before any ...
Page 65
Register Description 9.3.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the ...
Page 66
Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void) { uchar temp; } 8011O–AVR–07/10 ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot ...
Page 67
External Interrupts 10.1 Overview The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This ...
Page 68
If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it ...
Page 69
PCICR – Pin Change Interrupt Control Register Bit (0x68) Read/Write Initial Value • Bit 3 – PCIE3: Pin Change Interrupt Enable 3 When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set ...
Page 70
Bit 1 – PCIF1: Pin Change Interrupt Flag 1 When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), ...
Page 71
PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 ...
Page 72
I/O-Ports 11.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
Page 73
Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 11.2 Ports as General Digital I/O The ports are bi-directional I/O ports ...
Page 74
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
Page 75
Figure 11-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...
Page 76
Assembly Code Example C Code Example unsigned char i; Note: 11.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
Page 77
Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
Page 78
Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...
Page 79
Table 11-2 ure 11-5 in the modules having the alternate function. Table 11-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
Page 80
Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 11-3. Port Pin PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 • ADC7:0/PCINT7:0 – Port A, Bit 7:0 ADC7:0, Analog to Digital Converter, ...
Page 81
Table 11-4 on page 81 overriding signals shown in Table 11-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 11-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8011O–AVR–07/10 and Table ...
Page 82
Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 11-6. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • SCK/PCINT15 – Port B, ...
Page 83
MOSI/PCINT13 – Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When ...
Page 84
T0/XCK0/PCINT8, Bit 0 T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates ...
Page 85
Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 11-9. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 • TOSC2/PCINT23 – Port C, Bit 7 TOSC2, Timer Oscillator pin 2. ...
Page 86
TMS/PCINT19 – Port C, Bit 3 TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt source. • TCK/PCINT18 – Port C, Bit 2 TCK, JTAG Test Clock. PCINT18, ...
Page 87
Table 11-11. Overriding Signals for Alternate Functions in PC3:PC0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 11.3.4 Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 11-12. Port ...
Page 88
The alternate pin configuration is as follows: • OC2A/PCINT31 – Port D, Bit 7 OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be ...
Page 89
INT0/RXD1/PCINT26 – Port D, Bit 2 INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is ...
Page 90
Table 11-14. Overriding Signals for Alternate Functions in PD3:PD0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: 8011O–AVR–07/10 PD3/INT1/TXD1/ PD2/INT0/RXD1/ PCINT27 PCINT26 TXEN1 RXEN1 0 PORTD2 • PUD TXEN1 RXEN1 1 0 TXEN1 0 TXD1 ...
Page 91
Register Description 11.3.5 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn ...
Page 92
PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 11.3.13 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 11.3.14 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...
Page 93
Timer/Counter0 with PWM 12.1 Features • Two Independent Output Compare Units • Double Buffered Output Compare Registers • Clear Timer on Compare Match (Auto Reload) • Glitch Free, Phase Correct Pulse Width Modulator (PWM) • Variable PWM Period ...
Page 94
The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...
Page 95
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = ...
Page 96
Figure 12-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
Page 97
Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting. The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of ...
Page 98
Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...
Page 99
Figure 12-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be ...
Page 100
PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 12-6. Fast PWM ...
Page 101
OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 12.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM02:0 = ...
Page 102
OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See be visible on the port pin if the data direction for the port pin ...
Page 103
Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 12-10 mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx ...
Page 104
Register Description 12.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...
Page 105
Table 12-4. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B1:0 bits are set, the OC0B output ...
Page 106
Table 12-7 on page 106 to phase correct PWM mode. Table 12-7. COM0B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • ...
Page 107
TCCR0B – Timer/Counter Control Register B Bit 0x25 (0x45) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility ...
Page 108
Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 12-9. CS02 external pin modes are used for ...
Page 109
OCR0B – Output Compare Register B Bit 0x28 (0x48) Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output ...
Page 110
Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware ...
Page 111
Timer/Counter1 with PWM 13.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear ...
Page 112
Figure 13-1. 16-bit Timer/Counter Block Diagram Note: 13.2.1 Registers The Timer/Counter (TCNTn), Output Compare Registers (OCRnA/B/C), and Input Capture Reg- ister (ICRn) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...
Page 113
See Section “13.7” on page Flag (OCFnA/B/C) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input Capture ...
Page 114
Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNTn value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
Page 115
The following code examples show how atomic read of the TCNTn Register contents. Reading any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_ReadTCNTn: C Code Example unsigned ...
Page 116
The following code examples show how atomic write of the TCNTn Register contents. Writing any of the OCRnA/B/C or ICRn Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNTn: C Code Example void ...
Page 117
Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 13-2 Figure 13-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...
Page 118
The Timer/Counter Overflow Flag (TOVn) is set according to the mode of operation selected by the WGMn3:0 bits. TOVn can be used for generating a CPU interrupt. 13.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...
Page 119
TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be written to the ICRnH I/O location before the low byte is written ...
Page 120
I/O bit location). For measuring frequency only, the clearing of the ICFn Flag is not required (if an interrupt handler is used). 13.7 Output Compare Units The 16-bit comparator continuously compares ...
Page 121
PWM pulses, thereby making the out- put glitch-free. The OCRnx Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCRnx Buffer ...
Page 122
Compare Match Output Unit The Compare Output mode (COMnx1:0) bits have two functions. The Waveform Generator uses the COMnx1:0 bits for defining the Output Compare (OCnx) state at the next compare match. Secondly the COMnx1:0 bits control the OCnx ...
Page 123
Compare Output Mode and Waveform Generation The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COMnx1 tells the Waveform Generator that no action on the OCnx Register ...
Page 124
The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCRnA or ICRn, and then counter (TCNTn) is cleared. Figure 13-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...
Page 125
PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), ...
Page 126
ICRn value written is lower than the current value of TCNTn. The result will then be that the counter will ...
Page 127
However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-bit, 9-bit, or 10-bit, or defined by ...
Page 128
OCRnx Registers are written. As the third period shown in TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update ...
Page 129
OCRnA set to MAX). The PWM resolution in bits can be calculated using the following equation: In phase and frequency correct PWM mode the counter is incremented until the counter value matches either ...
Page 130
Using the ICRn Register for defining TOP works well when using fixed TOP values. By using ICRn, the OCRnA Register is free to be used for generating a PWM output on OCnA. However, if the base PWM frequency is actively ...
Page 131
Figure 13-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f Figure 13-12 frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by ...
Page 132
Figure 13-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF n 13.11 Register Description 13.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 ...
Page 133
Table 13-3 on page 133 the fast PWM mode. Table 13-3. COMnA1/COMnB1 Note: Table 13-4 on page 133 the phase correct or the phase and frequency correct, PWM mode. Table 13-4. COMnA1/COMnB1 Note: • Bit 1:0 – WGMn1:0: Waveform Generation ...
Page 134
Table 13-5. Waveform Generation Mode Bit Description WGMn2 WGMn1 Mode WGMn3 (CTCn) (PWMn1 ...
Page 135
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...
Page 136
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCRnA as TOP. The FOCnA/FOCnB bits are always read as zero. 13.11.4 TCNT1H and TCNT1L –Timer/Counter1 Bit ...
Page 137
ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin (or optionally on the Analog Comparator ...
Page 138
TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, ...
Page 139
Timer/Counter2 with PWM and Asynchronous Operation 14.1 Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and ...
Page 140
Registers The Timer/Counter (TCNT2) and Output Compare Register (OCR2A and OCR2B) are 8-bit reg- isters. Interrupt request (abbreviated to Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR2). All interrupts are individually masked with the Timer ...
Page 141
Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 14-2 shows a block diagram of the counter and its surrounding environment. Figure 14-2. Counter Unit Block Diagram Signal description (internal signals): count direction ...
Page 142
WGM22:0 bits and Compare Output mode (COM2x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ...
Page 143
Using the Output Compare Unit Since writing TCNT2 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT2 when using the Output Compare channel, independently of whether ...
Page 144
Register bit for the OC2x pin (DDR_OC2x) must be set as output before the OC2x value is visi- ble on the pin. The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin ...
Page 145
The timing diagram for the CTC mode is shown in (TCNT2) increases until a compare match occurs between TCNT2 and OCR2A, and then coun- ter (TCNT2) is cleared. Figure 14-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt ...
Page 146
DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The ...
Page 147
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of ...
Page 148
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM2x1:0 to ...
Page 149
Figure 14-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 14-9 on page 149 Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 14-10 on page 149 Figure 14-10. Timer/Counter Timing Diagram, ...
Page 150
Figure 14-11 on page 150 Figure 14-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- (clk TCNTn (CTC) OCRnx OCFnx 14.9 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When ...
Page 151
OCR2xUB bit returns to zero, the device will never receive a compare match interrupt, and the MCU will not wake up. • If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction ...
Page 152
Timer/Counter Prescaler Figure 14-12. Prescaler for Timer/Counter2 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, ...
Page 153
When OC2A is connected to the pin, the function of the COM2A1:0 bits depends on the WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-2. COM2A1 Table 14-3 mode. Table 14-3. ...
Page 154
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-5. COM2B1 Table 14-6 mode. Table 14-6. ...
Page 155
Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of wave- form ...
Page 156
Bit 6 – FOC2B: Force Output Compare B The FOC2B bit is only active when the WGM bits specify a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2B is ...
Page 157
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers. 14.11.4 OCR2A – Output Compare Register A Bit (0xB3) Read/Write Initial ...
Page 158
Bit 2 – OCR2BUB: Output Compare Register2 Update Busy When Timer/Counter2 operates asynchronously and OCR2B is written, this bit becomes set. When OCR2B has been updated from the temporary storage register, this bit is cleared by hard- ware. A ...
Page 159
TIFR2 – Timer/Counter2 Interrupt Flag Register Bit 0x17 (0x37) Read/Write Initial Value • Bit 2 – OCF2B: Output Compare Flag 2 B The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data ...
Page 160
Bit 0 - PSRSYNC: Prescaler Reset When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except ifthe TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share ...
Page 161
SPI – Serial Peripheral Interface 15.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
Page 162
The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...
Page 163
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 15-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...
Page 164
Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8011O–AVR–07/10 (1) ; Set MOSI and SCK output, all others input r17,(1<<DD_MOSI)|(1<<DD_SCK) ldi out DDR_SPI,r17 ; Enable SPI, Master, set clock ...
Page 165
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8011O–AVR–07/10 (1) ; ...
Page 166
SS Pin Functionality 15.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...
Page 167
Table 15-2. SPI Mode Figure 15-3. SPI Transfer Format with CPHA = 0 Figure 15-4. SPI Transfer Format with CPHA = 1 8011O–AVR–07/10 SPI Modes Conditions 0 CPOL=0, CPHA=0 1 CPOL=0, CPHA=1 2 CPOL=1, CPHA=0 3 CPOL=1, CPHA=1 SCK (CPOL ...
Page 168
Register Description 15.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...
Page 169
Bits 1:0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK ...
Page 170
SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...
Page 171
USART 16.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...
Page 172
Figure 16-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...
Page 173
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCKn pin is only active when using synchronous ...
Page 174
Table 16-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 194. 16.4.2 Double ...
Page 175
CPU clock period delay and therefore the maximum external XCKn clock frequency is limited by the following equation: Note that f add some margin to avoid possible loss of data due to frequency variations. 16.4.4 Synchronous Clock ...
Page 176
Figure 16-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing ...
Page 177
Note that the TXCn Flag must be cleared before each transmission (before UDRn is written used for this purpose. The following simple USART initialization code examples ...
Page 178
Sending Frames with Data Bit A data transmission is initiated by loading the transmit buffer with the data to be transmitted. The CPU can load the transmit buffer by writing to the UDRn I/O location. The ...
Page 179
Assembly Code Example USART_Transmit: C Code Example void USART_Transmit( unsigned int data ) { } Notes: The ninth bit can be used for indicating an address frame when using multi processor communi- cation mode or for other protocol handling as ...
Page 180
Data Register Empty interrupt routine must either write new data to UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new interrupt will occur once the interrupt routine terminates. The ...
Page 181
Assembly Code Example USART_Receive: C Code Example unsigned char USART_Receive( void ) { } Note: The function simply waits for data to be present in the receive buffer by checking the RXCn Flag, before reading the buffer and returning the ...
Page 182
Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...
Page 183
Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...
Page 184
The Parity Error (UPEn) Flag can then be read by software to check if the frame had a Parity Error. The UPEn bit is set if the next character that can be read ...
Page 185
Double Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (that is, no communication activity). Figure 16-5. Start Bit Sampling Sample (U2X = 0) ...
Page 186
Figure 16-7. Stop Bit Sampling and Next Start Bit Sampling The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop bit is registered to have a logic 0 ...
Page 187
Table 16-2. # (Data+Parity Bit) Table 16-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...
Page 188
When the frame type bit is zero the frame is a data frame. The Multi-processor Communication mode enables several slave MCUs to ...
Page 189
Register Description 16.11.1 UDRn – USART I/O Data Register n Bit Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDRn. ...
Page 190
Data Register Empty interrupt (see description of the UDRIEn bit).UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error This bit is set if the next character in the receive ...
Page 191
Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable n Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, ...
Page 192
Bits 5:4 – UPMn1:0: Parity Mode These bits enable and set type of parity generation and check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits within each frame. The Receiver will ...
Page 193
Bit 0 – UCPOLn: Clock Polarity This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets the relationship between data output change and data input sample, and ...
Page 194
Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRR settings in UBRR values which yield an actual baud rate differing ...
Page 195
Table 16-10. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
Page 196
Table 16-11. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...
Page 197
Table 16-12. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
Page 198
USART in SPI Mode 17.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...
Page 199
Note: BAUD f OSC UBRRn 17.4 SPI Data Modes and Timing There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams ...
Page 200
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for ...