ATmega644P Atmel Corporation, ATmega644P Datasheet - Page 157

• Manufacturer Part Number: ATmega644P
• Manufacturer: Atmel Corporation

Specifications of ATmega644P

• Flash (kbytes): 64 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.11.4
14.11.5
14.11.6
8011O–AVR–07/10
OCR2A – Output Compare Register A
OCR2B – Output Compare Register B
ASSR – Asynchronous Status Register
Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running,
introduces a risk of missing a Compare Match between TCNT2 and the OCR2x Registers.
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2A pin.
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC2B pin.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input buf-
fer is enabled and an external clock can be input on Timer Oscillator 1 (TOSC1) pin instead of a
32 kHz crystal. Writing to EXCLK should be done before asynchronous operation is selected.
Note that the crystal Oscillator will only run when this bit is zero.
• Bit 5 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter2 is clocked from the I/O clock, clk
written to one, Timer/Counter2 is clocked from a crystal Oscillator connected to the Timer Oscil-
lator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2A,
OCR2B, TCCR2A and TCCR2B might be corrupted.
• Bit 4 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set.
When TCNT2 has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 3 – OCR2AUB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2A is written, this bit becomes set.
When OCR2A has been updated from the temporary storage register, this bit is cleared by hard-
ware. A logical zero in this bit indicates that OCR2A is ready to be updated with a new value.
Bit
(0xB3)
Read/Write
Initial Value
Bit
(0xB4)
Read/Write
Initial Value
Bit
(0xB6)
Read/Write
Initial Value
R
7
–
0
R/W
R/W
7
0
7
0
EXCLK
R/W
6
0
R/W
R/W
6
0
6
0
R/W
AS2
5
0
R/W
R/W
TCN2UB
5
0
5
0
R
4
0
R/W
R/W
4
0
4
0
OCR2AUB
OCR2A[7:0]
OCR2B[7:0]
R
3
0
ATmega164P/324P/644P
R/W
R/W
3
0
3
0
OCR2BUB
R
2
0
R/W
R/W
2
0
2
0
TCR2AUB
R/W
R/W
R
1
0
1
0
1
0
TCR2BUB
I/O
R/W
R/W
0
0
0
0
. When AS2 is
R
0
0
OCR2A
OCR2B
ASSR
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