ATtiny2313A Atmel Corporation, ATtiny2313A Datasheet
ATtiny2313A
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ATtiny2313A Summary of contents
Page 1
... Low Power Consumption – Active Mode • 190 µA at 1.8V and 1MHz – Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Rev. 8246B–AVR–09/11 ...
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... Pin Configurations Figure 1-1. ATtiny2313A/4313 2 Pinout ATtiny2313A/4313 PDIP/SOIC (PCINT10/RESET/dW) PA2 (PCINT11/RXD) PD0 (PCINT12/TXD) PD1 (PCINT9/XTAL2) PA1 (PCINT8/CLKI/XTAL1) PA0 (PCINT13/CKOUT/XCK/INT0) PD2 (PCINT14/INT1) PD3 (PCINT15/T0) PD4 (PCINT16/OC0B/T1) PD5 GND MLF/VQFN (PCINT12/TXD) PD1 1 (PCINT9/XTAL2) PA1 2 (PCINT8/CLKI/XTAL1) PA0 3 (PCINT13/CKOUT/XCK/INT0) PD2 4 (PCINT14/INT1) PD3 5 NOTE: Bottom pad should be soldered to ground. ...
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... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 67. ...
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... XTAL2 Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1. ATtiny2313A/4313 4 8246B–AVR–09/11 ...
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... Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313A/4313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. ...
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... Note that not all AVR devices include an extended I/O map. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8246B–AVR–09/11 ATtiny2313A/4313 7 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. ATtiny2313A/4313 8 Block Diagram of the AVR Architecture ...
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... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8246B–AVR–09/11 ATtiny2313A/4313 9 ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. ATtiny2313A/4313 ...
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... Purpose R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4-2, each register is also assigned a data memory address, mapping them ATtiny2313A/4313 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Figure 4-4 vard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ATtiny2313A/4313 12 The X-, Y-, and Z-registers 15 XH ...
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... Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back “Interrupts” on page 48 for more information. ATtiny2313A/4313 “Interrupts” on page 48. The list also T4 ...
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... C Code Example __enable_interrupt(); /* set Global Interrupt Enable */ __sleep(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ ATtiny2313A/4313 14 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. 8246B–AVR–09/11 ATtiny2313A/4313 15 ...
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... All memory spaces are linear and regular. 5.1 Program Memory (Flash) ATtiny2313A/4313 contains 2/4K byte of on-chip, in-system reprogrammable Flash memory for program storage. Flash memories are non-volatile, i.e. they retain stored information even when not powered. Since all AVR instructions are bits wide, the Flash is organized as 1024/2048 x 16 bits. ...
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... I/O registers starting at 0x20. See “Instruction Set Summary” on page ATtiny2313A/4313 also contains three general purpose I/O registers that can be used for storing any information. See GPIOR0, GPIOR1 and GPIOR2 in These general purpose I/O registers are particularly useful for storing global variables and status 8246B– ...
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... I/O register files and the data memory. Internal SRAM is accessed in two clk Figure 5-2. 5.3 Data Memory (EEPROM) ATtiny2313A/4313 contains 128 bytes of non-volatile data memory. This EEPROM is organized as a separate data space, in which single bytes can be read and written. All access registers are located in the I/O space. ATtiny2313A/4313 18 “ ...
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... Read data from the EEPROM Data Register (EEDR). 8246B–AVR–09/11 Table Size of Non-Volatile Data Memory (EEPROM). EEPROM Size 128B 256B “OSCCAL – Oscillator Calibration Register” on 20. ATtiny2313A/4313 5-3, below. Address Range 0x00 – 0x7F 0x00 – 0xFF , is likely to rise or fall slowly CC Table 5-4 on page 24. Write and erase ...
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... CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. At low supply voltages data in EEPROM can be corrupted in two ways: ATtiny2313A/4313 20 , the EEPROM data can be corrupted because the supply voltage is CC 8246B– ...
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... Set up address (r18:r17) in address registers out EEARH, r18 out EEARL, r17 ; Write data (r19) to data register out EEDR, r19 ; Write logical one to EEMPE sbi EECR, EEMPE ; Start eeprom write by setting EEPE sbi EECR, EEPE ret See “Code Examples” on page 7. ATtiny2313A/4313 can ...
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... Set up address (r18:r17) in address registers out EEARH, r18 out EEARL, r17 ; Start eeprom read by writing EERE sbi EECR, EERE ; Read data from data register in ret Note: ATtiny2313A/4313 22 See “Code Examples” on page 7. r16, EEDR See “Code Examples” on page 7. 8246B–AVR–09/11 ...
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... Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny4313. In devices with less EEPROM, i.e. ATtiny2313A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...
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... When EEPE has been set, the CPU is halted for two cycles before the next instruction is exe- cuted. After the write access time has elapsed, the EEPE bit is cleared by hardware. Note that an EEPROM write operation blocks all software programming of Flash, fuse bits, and lock bits. ATtiny2313A/4313 ...
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... Read/Write Initial Value 8246B–AVR–09/ MSB R/W R/W R/W R/W R MSB R/W R/W R/W R/W R MSB R/W R/W R/W R/W R ATtiny2313A/4313 LSB GPIOR2 R/W R/W R LSB GPIOR1 R/W R/W R LSB GPIOR0 R/W R/W R ...
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... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATtiny2313A/4313 26 presents the principal clock systems in the AVR and their distribution. All of the clocks 34. Clock Distribution General I/O ...
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... To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. 8246B–AVR–09/11 Device Clocking Select page 27) page 29) page 1. For all fuses “1” means unprogrammed while “0” means programmed. 200), but routing the clock signal from the internal oscillator directly to ATtiny2313A/4313 CKSEL3..0 0000 page 28) 0010 page 28) 0100 0110 ...
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... Oscillator and 25°C, this calibration gives a frequency within ± 10% of the nominal fre- quency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given V When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the ATtiny2313A/4313 28 External Clock Drive Configuration NC ...
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... Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- Additional Delay from down and Power-save the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + ensure programming mode can be entered. ATtiny2313A/4313 181. Nominal Frequency 4.0 MHz (1) 8.0 MHz Reset Recommended Usage (1) ...
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... The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-6. CKSEL3..1 (1) 100 101 110 111 Note: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 6-7. ATtiny2313A/4313 30 Table 6-6 on page Crystal Oscillator Connections C2 C1 Crystal Oscillator Operating Modes Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8 ...
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... Notes: 6.3 System Clock Prescaler The ATtiny2313A/4313 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in ATtiny2313A/4313 and it will always read zero. • Bits 6:0 – CAL[6:0]: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen ...
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... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...
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... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 26 ATtiny2313A/4313. The figure is helpful in selecting an appropriate sleep mode. shows the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...
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... This will reduce power consumption in Idle level has dropped during the sleep period. CC 38. Writing this bit to one turns off BOD in 38. “PRR – Power Reduction Register” on page ATtiny2313A/4313 Table 20-4 on page “BODCR “BODCR – 37, pro- 35 ...
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... See the section Input Enable and Sleep Modes” on page 58 buffer is enabled and the input signal is left floating or has an analog signal level close to V the input buffer will use excessive power. ATtiny2313A/4313 36 “Effect of Power Reduction” on page 206 “Analog Comparator” on page 168 “ ...
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... Sleep Mode Select SM0 Sleep Mode 0 Idle 1 Power-down 0 Standby 1 Power-down Standby mode is only recommended for use with external crystals or resonators – – – ATtiny2313A/4313 for details ISC11 ISC10 ISC01 ISC00 R/W R/W R/W R Table 7- – ...
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... BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles. • Bit 0 – BODSE: BOD Sleep Enable The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by a timed sequence. ATtiny2313A/4313 — ...
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... Electrical parameters of the Table 22-3 on page 201. Reset Logic Power-on Reset Circuit Brown-out Reset Circuit Pull-up Resistor SPIKE FILTER Watchdog Oscillator Clock CK Generator CKSEL[3:0] SUT[1:0] ATtiny2313A/4313 DATA BUS MCU Status Register (MCUSR) Delay Counters TIMEOUT “Clock Sources” on page 27. 39 ...
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... Reset Sources The ATtiny2313A/4313 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled • ...
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... Figure 8-4. 8.2.3 Brown-out Detection ATtiny2313A/4313 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Figure 8-6. 8.3 Internal Voltage Reference ATtiny2313A/4313 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator. The bandgap voltage varies with supply voltage and temperature. 8.3.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used ...
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... WATCHDOG RESET WDP0 WDP1 WDP2 WDP3 WDE written to WDE regardless of the previous value of the WDE bit bits as desired, but with the WDCE bit cleared ATtiny2313A/4313 Table 8-1 for details. How to Disable the How to Change Time- WDT out Timed sequence No limitations Always enabled ...
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... Write logical one to WDCE and WDE */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; } Note: ATtiny2313A/4313 44 WDE always is set, the WDE must be written to one to start the timed sequence desired, but with the WDCE bit cleared. The value written to the WDE bit is irrelevant (1) r16, (0< ...
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... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
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... To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure. Note: ATtiny2313A/4313 46 Watchdog Timer Configuration WDIE Watchdog Timer State ...
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... If selected, one of the valid settings below 0b1010 will be used. ATtiny2313A/4313 Typical Time-out at Cycles cycles cycles cycles 64 ms 16K cycles 0.125 s 32K cycles 0.25 s 64K cycles 0.5 s 128K cycles 1.0 s 256K cycles 2 ...
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... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313A/4313. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors The interrupt vectors of ATtiny2313A/4313 are described in Table 9-1. Vector No ...
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... The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313 shown below: Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 ; 0x0013 0x0014 0x0015 0x0016 ...
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... SLEEP command. 9.2.2 Pin Change Interrupt Timing A timing example of a pin change interrupt is shown in Figure 9-1. PCINT(0) PCINT(0) pin_lat pin_sync pcint_in_(0) pcint_syn pcint_setflag PCIF ATtiny2313A/4313 50 26. Timing of pin change interrupts pin_lat pcint_in_( pin_sync LE clk PCINT(0) in PCMSK(x) clk Figure 9-1 ...
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... The value on the INT0 pin is sampled before detecting edges. Interrupt 0 Sense Control ISC00 Description 0 The low level of INT0 generates an interrupt request. 1 Any logical change on INT0 generates an interrupt request. 0 The falling edge of INT0 generates an interrupt request. 1 The rising edge of INT0 generates an interrupt request. ATtiny2313A/4313 ISC10 ISC01 ISC00 MCUCR R/W R/W R/W ...
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... When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT10..8 pin will cause an inter- rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT10..8 pins are enabled individually by the PCMSK1 Register. ATtiny2313A/4313 ...
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... These bits are reserved and will always read as zero. 8246B–AVR–09/ INTF1 INTF0 PCIF0 PCIF2 R/W R/W R/W R – PCINT17 PCINT16 PCINT15 R R/W R/W R ATtiny2313A/4313 PCIF1 – – – R PCINT14 PCINT13 PCINT12 PCINT11 R/W R/W R/W R GIFR ...
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... Bits 7..0 – PCINT7..0: Pin Change Enable Mask 7..0 Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. ATtiny2313A/4313 – ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin “Register Description” on page 60. Refer to the individual module sections for a full description of the alter- ATtiny2313A/4313 Figure 10-1 on page 55. See “Electri Logic See Figure "General Digital I/O" for Details 69. “ ...
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... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATtiny2313A/4313 56 (1) Pxn ...
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... Input 0 X Output 1 X Output Figure 10-2 on page SYSTEM CLK INSTRUCTIONS XXX SYNC LATCH PINxn r17 ATtiny2313A/4313 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 56, the PINxn Register bit and the preced- and t respectively ...
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... Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is ATtiny2313A/4313 58 Figure 10-4 on page 58. The out instruction sets the “SYNC LATCH” signal at the ...
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... Define pull-ups and set outputs high */ /* Define directions for port pins */ PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; ... 1. See “Code Examples” on page 7. ATtiny2313A/4313 59 ...
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... DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: The illustration in the figure above serves as a generic description applicable to all port pins in the AVR microcontroller family. Some overriding signals may not be present in all port pins. ATtiny2313A/4313 60 (1) PUOExn PUOVxn 1 0 ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/Output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATtiny2313A/4313 Fig- 61 ...
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... I/O pin with pull-up enabled and becomes the communication gateway between target and emulator. • PCINT10: Pin Change Interrupt source 10. The PA2 pin can serve as an external interrupt source for pin change interrupt 1. ATtiny2313A/4313 62 Port A Pins Alternate Functions Port Pin ...
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... AIN1: Analog Comparator, Negative Input PB1 PCINT1: Pin Change Interrupt 0, Source 1 OC0A:: Timer/Counter0 Compare Match AOutput PB2 PCINT2: Pin Change Interrupt 0, Source 2 OC1A: Timer/Counter1 Compare Match A Output PB3 PCINT3: Pin Change Interrupt 0, Source 3 ATtiny2313A/4313 PA0/XTAL1/PCINT8 (3) (4) EXT_CLOCK + EXT_OSC 0 (3) (4) EXT_CLOCK + EXT_OSC ...
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... Port B, Bit 4 – OC1B/PCINT4 • OC1B: Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB4 set ATtiny2313A/4313 64 Port B Pins Alternate Functions Port Pin ...
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... USCK: Three-wire mode Universal Serial Interface Clock. • SCL: Two-wire mode Serial Clock for USI Two-wire mode. • PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source for pin change interrupt 0. 8246B–AVR–09/11 ATtiny2313A/4313 65 ...
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... PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny2313A/4313 66 and Table 10-7 relate the alternate functions of Port B to the overriding signals Figure 10-5 on page 60. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the Overriding Signals for Alternate Functions in PB7..PB4 PB7/USCK/ SCL/PCINT7 ...
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... External Interrupt 1 Input PD3 PCINT14:Pin Change Interrupt 2, Source 14 T0: Timer/Counter0 Clock Source PD4 PCINT15:Pin Change Interrupt 2, Source 15 OC0B: Timer/Counter0 Compare Match B output PD5 T1: Timer/Counter1 Clock Source PCINT16:Pin Change Interrupt 2, Source 16 ICPI: Timer/Counter1 Input Capture Pin PD6 PCINT17:Pin Change Interrupt 2, Source 17 ATtiny2313A/4313 Table 10-8.. 67 ...
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... Table 10-9 shown in Table 10-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO ATtiny2313A/4313 68 and Table 10-10 relates the alternate functions of Port D to the overriding signals Figure 10-5 on page 60. Overriding Signals for Alternate Functions PD6..PD4 PD6/ICPI/PCINT17 PD5/OC1B/T1/PCINT16 ...
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... – – – – ATtiny2313A/4313 PD1/TXD/ PCINT12 PD0/RXD/PCINT11 TXD_OE RXD_OE 0 PORTD0 • PUD TXD_OE RXD_EN 1 0 TXD_OE 0 TXD_PVOV PCINT12 PCINT11 PCINT12 PCINT11 PCINT12 RXD Input/PCINT11 – – 3 ...
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... PORTD – Port D Data Register Bit 0x12 (0x32) Read/Write Initial Value 10.3.9 DDRD – Port D Data Direction Register Bit 0x11 (0x31) Read/Write Initial Value 10.3.10 PIND – Port D Input Pins Address Bit 0x10 (0x30) Read/Write Initial Value ATtiny2313A/4313 – – – – N/A N/A N/A ...
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... Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 8246B–AVR–09/11 “Pinout ATtiny2313A/4313” on page “Register Description” on page 82. Count ...
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... Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. 11-2 shows a block diagram of the counter and its surroundings. Figure 11-2. Counter Unit Block Diagram ATtiny2313A/4313 72 See “Output Compare Unit” on page 73. Table 11-1 are also used extensively throughout the document. ...
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... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 97. shows a block diagram of the Output Compare unit. ATtiny2313A/4313 in the following. T0 “Modes of Opera- “Modes of Operation” on page 97). 73 ...
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... TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform ATtiny2313A/4313 74 DATA BUS OCRnx ...
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... The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 8246B–AVR–09/11 COMnx1 Waveform COMnx0 Generator FOCn clk I/O See “Register Description” on page 82. ATtiny2313A/4313 Figure 11-4 shows a simplified OCnx PORT D ...
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... This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting external events. The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. ATtiny2313A/4313 76 Figure 11-3 on page 66, and for phase correct PWM refer to Figure 74 ...
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... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8246B–AVR–09/ clk_I ------------------------------------------------- - ⋅ ⋅ ( OCnx OCRnx ATtiny2313A/4313 OCnx Interrupt Flag Set (COMnx1 OC0 ) 77 = ...
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... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f ATtiny2313A/4313 78 Figure 11-4. The TCNT0 value is in the timing diagram shown as a his- ...
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... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 8246B–AVR–09/11 11-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATtiny2313A/4313 OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
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... MAX value in all modes other than phase correct PWM mode. Figure 11-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk I/O TCNTn TOVn Figure 11-9 on page 81 ATtiny2313A/4313 80 Table 10-7 on page f OCnxPCPWM Figure 11-7 on page 79 Figure 11-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn ...
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... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATtiny2313A/4313 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
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... When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 11-2. COM0A1 Table 11-3 mode. Table 11-3. COM0A1 Note: ATtiny2313A/4313 COM0A1 COM0A0 COM0B1 COM0B0 R/W R/W R/W R ...
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... Set OC0B on Compare Match, clear OC0B at TOP 1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATtiny2313A/4313 (1) “Phase Correct PWM Mode” on (1) “ ...
Page 84
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 85
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 86
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC0B pin. ATtiny2313A/4313 86 Clock Select Bit Description CS01 CS00 Description ...
Page 87
... Initial Value • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 88
... OCR0A – Output Compare Register0 A. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable), and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed. ATtiny2313A/4313 88 Table 84. ...
Page 89
... I/O pins, refer to ters, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 12-1. 16-bit Timer/Counter Block Diagram Note: 8246B–AVR–09/11 “Pinout ATtiny2313A/4313” on page “Register Description” on page Count Clear Control Logic Direction ...
Page 90
... The following definitions are used extensively throughout the section: Table 12-1. Constant BOTTOM MAX TOP ATtiny2313A/4313 90 94.. The compare match event will also set the Compare Match 168.) The Input Capture unit includes a digital filtering unit (Noise Definitions Description The counter reaches BOTTOM when it becomes 0x0000 ...
Page 91
... TEMP (8-bit) Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction TCNTn (16-bit Counter) Increment or decrement TCNT1 by 1. Select between increment and decrement. Clear TCNT1 (set all bits to zero). ATtiny2313A/4313 118. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) ...
Page 92
... Alternatively the time-stamps can be used for creating a log of the events. The Input Capture unit is illustrated by the block diagram shown in the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. ATtiny2313A/4313 92 Timer/Counter clock Signalize that TCNT1 has reached maximum value ...
Page 93
... DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn 107. ATtiny2313A/4313 (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler Detector “Accessing 16-bit Registers” ...
Page 94
... Waveform Generation mode (WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation ATtiny2313A/4313 94 (Figure 13-1 on page (See “Modes of Operation” on page 118) ...
Page 95
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATtiny2313A/4313 (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 COMnx1:0 ...
Page 96
... PORT) that are affected by the COM1x1:0 bits are shown. When referring to the OC1x state, the reference is for the internal OC1x Register, not the OC1x pin system reset occur, the OC1x Register is reset to “0”. ATtiny2313A/4313 96 107. “Accessing 16-bit Registers” ...
Page 97
... The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output 8246B–AVR–09/11 Waveform Generator I/O See “Register Description” on page 111. Table 12-2 on page ATtiny2313A/4313 OCnx PORT ...
Page 98
... It also simplifies the opera- tion of counting external events. The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. ATtiny2313A/4313 98 96.) “Timer/Counter Timing Diagrams” on page Figure 12-6 ...
Page 99
... OCR1A is set to zero (0x0000). The waveform frequency clk_I --------------------------------------------------- ⋅ ⋅ ( OCnA 2 N ATtiny2313A/4313 OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I OCRnA + 99 ...
Page 100
... ICR1 value written is lower than the current value of TCNT1. The result will then be that the counter will miss the compare match at the TOP value. The counter will then have to count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur. ATtiny2313A/4313 100 ( ...
Page 101
... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 8246B–AVR–09/11 ATtiny2313A/4313 Table 12-2 on page f clk_I/O f ...
Page 102
... TOP actively while the Timer/Counter is running in the phase correct mode can result in an unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg- ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This ATtiny2313A/4313 102 ( ...
Page 103
... ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: 8246B–AVR–09/11 f OCnxPCPWM and Figure 12-9 on page 104). log R = ---------------------------------- - PFCPWM ATtiny2313A/4313 Table 12-3 on page f clk_I/O = --------------------------- - ⋅ ⋅ TOP ( ) 1 TOP + ...
Page 104
... PWM frequency is actively changed by changing the TOP value, using the OCR1A as TOP is clearly a better choice due to its double buffer feature. In phase and frequency correct PWM mode, the compare units allow generation of PWM wave- forms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and ATtiny2313A/4313 104 Figure 12-9 on page 1 ...
Page 105
... OCnxPFCPWM Figure 12-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATtiny2313A/4313 f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx + 2 OCRnx Value Table 12-4 on ...
Page 106
... The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM. Figure 12-12. Timer/Counter Timing Diagram, no Prescaling (CTC and FPWM) (PC and PFC PWM) and ICFn Figure 12-13 ATtiny2313A/4313 106 clk I/O clk Tn /8) I/O ...
Page 107
... The same principle can be used directly for accessing 8246B–AVR–09/11 clk I/O clk Tn (clk /8) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) ATtiny2313A/4313 /8) clk_I/O TOP BOTTOM BOTTOM + 1 TOP TOP - 1 TOP - 2 New OCRnx Value 107 ...
Page 108
... Therefore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. ATtiny2313A/4313 108 (1) (1) 1. See “ ...
Page 109
... Restore global interrupt flag out SREG,r18 ret (1) unsigned char sreg; unsigned int i; /* Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; 1. See “Code Examples” on page 7. ATtiny2313A/4313 109 ...
Page 110
... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATtiny2313A/4313 110 (1) (1) 1. See “ ...
Page 111
... COM1A0/COM1B0 special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. Mode” on page 99. for more details. ATtiny2313A/4313 – – WGM11 WGM10 R R R/W R/W ...
Page 112
... Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. ATtiny2313A/4313 112 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase Compare Output Mode, Phase Correct and Phase and Frequency Correct ...
Page 113
... Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATtiny2313A/4313 Update of x TOP OCR1 at 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A BOTTOM ...
Page 114
... FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. ATtiny2313A/4313 114 and Figure 12-11 on page ...
Page 115
... R/W R OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R See “Accessing 16-bit Registers” on page 107. ATtiny2313A/4313 TCNT1H TCNT1L R/W R/W R/W R See “Accessing 16-bit OCR1AH OCR1AL R/W R/W R/W R OCR1BH OCR1BL ...
Page 116
... Bit 3 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page ATtiny2313A/4313 116 ...
Page 117
... ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. 8246B–AVR–09/ TOV1 OCF1A OCF1B – ICF1 R/W R/W R ATtiny2313A/4313 OCF0B TOV0 OCF0A TIFR R/W R/W R Table 12-5 on page 113 for the TOV1 117 ...
Page 118
... Figure 13-1. T1/T0 Pin Sampling Tn The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the T1/T0 pin to the counter is updated. ATtiny2313A/4313 118 ). Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization ...
Page 119
... Initial Value • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware ...
Page 120
... The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. A simplified block diagram of the USART Transmitter is shown in I/O Registers and I/O pins are shown in bold. Figure 14-1. USART Block Diagram Note: ATtiny2313A/4313 120 (1) UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) ...
Page 121
... Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper- ation. Double Speed (asynchronous mode only) is controlled by the U2X found in the UCSRA Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK 8246B–AVR–09/11 ATtiny2313A/4313 Figure 14-1) if the Buffer Registers 121 ...
Page 122
... UMSEL, U2X and DDR_XCK bits. Table 14-1 ing the UBRR value for each mode of operation using an internally generated clock source. ATtiny2313A/4313 122 shows a block diagram of the clock generation logic. UBRR ...
Page 123
... Baud rate (in bits per second, bps) System Oscillator clock frequency Contents of the UBRRH and UBRRL Registers, (0-4095) 142). Figure 14-2 for details. depends on the stability of the system clock source therefore recommended to osc ATtiny2313A/4313 Equation for Calculating (1) UBRR Value f f OSC OSC ...
Page 124
... When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. Figure 14-4 optional. Figure 14-4. Frame Formats ATtiny2313A/4313 124 XCK RxD / TxD XCK RxD / TxD ...
Page 125
... even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATtiny2313A/4313 … ⊕ ⊕ ⊕ ⊕ ⊕ … ⊕ ⊕ ⊕ ...
Page 126
... USART and given the function as the Transmitter’s serial output. The baud rate, mode of operation and frame format must be set up once before doing any transmissions. If syn- chronous operation is used, the clock on the XCK pin will be overridden and used as transmission clock. ATtiny2313A/4313 126 (1) UBRRH, r17 UBRRL, r16 r16, (1< ...
Page 127
... Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDR,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; 1. See “Code Examples” on page 7. ATtiny2313A/4313 127 ...
Page 128
... Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register Empty (UDRE) flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty, and cleared when the transmit buffer ATtiny2313A/4313 128 (1) ...
Page 129
... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo- ing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. 8246B–AVR–09/11 ATtiny2313A/4313 129 ...
Page 130
... If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR and UPE Status Flags as well. Read status from UCSRA, then data from UDR. Reading the UDR I/O location will ATtiny2313A/4313 130 (1) ...
Page 131
... Get status and 9th bit, then data */ /* from buffer */ status = UCSRA; resh = UCSRB; resl = UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “Code Examples” on page 7. ATtiny2313A/4313 131 ...
Page 132
... Bit Calculation” on page 125 14.7.5 Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected by the UPM0 bit. When enabled, the Parity ATtiny2313A/4313 132 and “Parity Checker” on page 132. ...
Page 133
... The sample rate is 16 times 8246B–AVR–09/11 (1) sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush (1) unsigned char dummy; while ( UCSRA & (1<<RXC) ) dummy = UDR; 1. See “Code Examples” on page 7. ATtiny2313A/4313 Figure 14-5 133 ...
Page 134
... RxD pin. The recovery process is then repeated until a complete frame is received. Including the first stop bit. Note that the Receiver only uses the first stop bit of a frame. ATtiny2313A/4313 134 RxD ...
Page 135
... R is the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 14-3 list the maximum receiver baud rate error that can be tolerated. Note ATtiny2313A/4313 STOP 1 (A) ( ...
Page 136
... If the Receiver is set up for frames with nine data bits, then the ninth bit (RXB8) is used for identifying address and data frames. When ATtiny2313A/4313 136 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode ...
Page 137
... UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB). 8246B–AVR–09/ RXB[7:0] TXB[7:0] R/W R/W R/W R/W R ATtiny2313A/4313 UDR (Read) UDR (Write) R/W R/W R 137 ...
Page 138
... This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive buffer is full (two characters new character waiting in the Receive Shift Register, and a new start bit is detected. This bit is valid until the receive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA. ATtiny2313A/4313 138 7 6 ...
Page 139
... Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port. 8246B–AVR–09/11 “Multi-processor Communication Mode” on page RXCIE TXCIE UDRIE RXEN TXEN R/W R/W R/W R ATtiny2313A/4313 136 UCSZ2 RXB8 TXB8 UCSRB R/W R 139 ...
Page 140
... The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting mismatch is detected, the UPE Flag in UCSRA will be set. Table 14-5. UPM1 ATtiny2313A/4313 140 ...
Page 141
... UBRR[7: R/W R/W R/W R ATtiny2313A/4313 Table 14-7. UCSZ0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit Received Data Sampled (Input on RxD Pin) Falling XCK Edge Rising XCK Edge ...
Page 142
... Max. 62.5 kbps 125 kbps 1. UBRR = 0, Error = 0.0% ATtiny2313A/4313 142 to Table 14-12. UBRR values which yield an actual baud rate differing less than 0.5% “Asynchronous Operational Range” on page BaudRate ⎛ Error[%] = ------------------------------------------------------- - 1 ⎝ BaudRate f = 1.8432 MHz osc ...
Page 143
... MHz osc U2X = 1 U2X = 0 Error UBRR Error 0.0% 103 0.2% 0.0% 51 0.2% 0.0% 25 0.2% 0.0% 16 2.1% 0.0% 12 0.2% 0.0% 8 -3.5% 0.0% 6 -7.0% 0.0% 3 8.5% 0.0% 2 8.5% 0.0% 1 8.5% 0.0% 0 8.5% -7.8% 0 0.0% -7.8% – – – – – 250 kbps ATtiny2313A/4313 f = 7.3728 MHz osc U2X = 1 U2X = 0 UBRR Error UBRR Error 207 0.2% 191 0.0% 103 0.2% 95 0.0% 51 0.2% 47 0.0% 34 -0.8% 31 0.0% 25 0.2% 23 0.0% 16 2.1% 15 0.0% 12 0.2% 11 0.0% 8 -3.5% 7 0.0% 6 -7.0% 5 0.0% 3 8. ...
Page 144
... Max. 0.5 Mbps 1. UBRR = 0, Error = 0.0% ATtiny2313A/4313 144 11.0592 f = osc U2X = 0 Error UBRR Error UBRR -0.1% 287 0.0% 0.2% 143 0.0% 0.2% 71 0.0% 0.6% 47 0.0% 0.2% 35 0.0% -0.8% 23 0.0% 0.2% 17 0.0% 2.1% 11 0.0% 0.2% 8 0.0% -3.5% 5 0.0% 8.5% 2 0.0% 0.0% 2 -7.8% 0.0% – – 0.0% – – ...
Page 145
... Max. 1. 8246B–AVR–09/11 (Continued) U2X = 0 UBRR Error 416 -0.1% 207 0.2% 103 0.2% 68 0.6% 51 0.2% 34 -0.8% 25 0.2% 16 2.1% 12 0.2% 8 -3.5% 3 8.5% 3 0.0% 1 0.0% 0 0.0% 1 Mbps UBRR = 0, Error = 0.0% ATtiny2313A/4313 f = 16.0000 MHz osc U2X = 1 UBRR Error 832 0.0% 416 -0.1% 207 0.2% 138 -0.1% 103 0.2% 68 0.6% 51 0.2% 34 -0.8% 25 0.2% 16 2.1% 8 -3.5% 7 0.0% 3 0.0% 1 0.0% 2 Mbps 145 ...
Page 146
... The internal clock generation used in MSPIM mode is identical to the USART synchronous mas- ter mode. The baud rate or UBRR setting can therefore be calculated using the same equations, see Table Table 15-1. Operating Mode Synchronous Master mode Note: ATtiny2313A/4313 146 = f /2) XCKmax CK 15-1: Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud ...
Page 147
... UCPOL=0 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) ATtiny2313A/4313 Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising) UCPOL=1 XCK ...
Page 148
... UDR is written used for this purpose. The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume polling (no interrupts enabled). The ATtiny2313A/4313 148 To ensure immediate initialization of the XCK output the baud-rate register (UBRR) must be zero at the time the transmitter is enabled ...
Page 149
... Set MSPI mode of operation and SPI data mode 0. */ UCSRC = (1<<UMSEL1)|(1<<UMSEL0)|(0<<UCPHA)|(0<<UCPOL); /* Enable receiver and transmitter. */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set baud rate IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRR = baud; 1. See ”Code Examples” on page 7. ATtiny2313A/4313 149 ...
Page 150
... The function then waits for data to be present in the receive buffer by checking the RXC Flag, before reading the buffer and returning the value. ATtiny2313A/4313 150 To keep the input buffer in sync with the number of data bytes transmitted, the UDR register must be read once for each byte transmitted ...
Page 151
... Wait for empty transmit buffer */ while ( !( UCSRA & (1<<UDRE Put data into buffer, sends the data */ UDR = data; /* Wait for data to be received */ while ( !(UCSRA & (1<<RXC Get and return received data from buffer */ return UDR; 1. See “Code Examples” on page 7. ATtiny2313A/4313 151 ...
Page 152
... Interrupt timing is not compatible. • Pin control differs due to the master only operation of the USART in MSPIM mode. A comparison of the USART in MSPIM mode and the SPI pins is shown in 152. Table 15-3. ATtiny2313A/4313 152 Comparison of USART in MSPIM mode and SPI pins. USART_MSPIM TxD ...
Page 153
... RXC bit in UCSRA is set. 8246B–AVR–09/ RXC TXC UDRE - R R RXCIE TXCIE UDRIE RXEN R/W R/W R/W R ATtiny2313A/4313 TXEN - - - R UCSRA ...
Page 154
... These bits select the mode of operation of the USART as shown in USART Control and Status Register C” on page 140 operation. The MSPIM is enabled when both UMSEL bits are set to one. The UDORD, UCPHA, and UCPOL can be set in the same write operation where the MSPIM is enabled. Table 15-4. ATtiny2313A/4313 154 ...
Page 155
... UBRRL and UBRRH – USART MSPIM Baud Rate Registers The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation. See “UBRRL and UBRRH – USART Baud Rate Registers” on page 141. 8246B–AVR–09/11 ATtiny2313A/4313 155 ...
Page 156
... The most significant bit of the USI Data Register is connected to one of two output pins (depend- ing on the mode configuration, see latch between the output of the USI Data Register and the output pin, which delays the change ATtiny2313A/4313 156 “Pinout ATtiny2313A/4313” on page “Register Description” on page 3 2 USIDR ...
Page 157
... USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR. 8246B–AVR–09/11 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SLAVE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MASTER shows two USI units operating in three-wire mode, one as Master and one as Slave. ATtiny2313A/4313 DO DI USCK DO DI USCK PORTxn 157 ...
Page 158
... The overflow interrupt will wake up the processor set to Idle mode. Depending on the protocol used the slave device can now set its output to high impedance. 16.3.2 SPI Master Operation Example The following code demonstrates how to use the USI module as a SPI Master: SPITransfer: <continues> ATtiny2313A/4313 158 ( Reference ) MSB 6 ...
Page 159
... USICR,r16 ; MSB out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 out USICR,r17 out USICR,r16 ; LSB out USICR,r17 in r16,USIDR ATtiny2313A/4313 159 ...
Page 160
... This means that the master must always check if the SCL line was actually released after it has generated a positive edge. Since the clock also increments the counter, a counter overflow can be used to indicate that the transfer is completed. The clock is generated by the master by toggling the USCK pin via the PORTA register. ATtiny2313A/4313 160 ldi r16,(1<<USIWM0)|(1<<USICS1) out ...
Page 161
... Bit4 Bit3 Bit2 Bit1 Bit0 MASTER ADDRESS R/W ACK (Figure 16-5), a bus transfer involves the following steps: ATtiny2313A/4313 VCC SDA SCL HOLD SCL Two-wire Clock Control Unit SDA SCL PORTxn DATA ACK DATA ACK Figure 16-6 on page ...
Page 162
... In two-wire slave mode the Two-wire Clock Con- trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the actual data rate in two-wire mode. ATtiny2313A/4313 162 Figure 16-6. The SDA line is delayed (in the range of 50 ...
Page 163
... The counter and USI 8246B–AVR–09/ USISIE USIOIE USIWM1 USIWM0 R/W R/W R/W R page 166 ATtiny2313A/4313 USICS1 USICS0 USICLK USITC R/W R page 165 for further details. ...
Page 164
... USICLK bit clocks both the USI Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external clocking and software clocking by the USITC strobe bit. ATtiny2313A/4313 164 Relationship between USIWM1:0 and USI Operation ...
Page 165
... External, negative edge USISIF USIOIF USIPF USIDC R/W R/W R ATtiny2313A/4313 4-bit Counter Clock Source No Clock Software clock strobe (USICLK) Timer/Counter0 Compare Match External, both edges External, both edges Software clock strobe (USITC) Software clock strobe (USITC) Table 16-2 USICNT3 USICNT2 ...
Page 166
... The shift operation can be synchronised to an external clock edge Timer/Counter0 Compare Match, or directly to software via the USICLK bit serial clock occurs at the same cycle the register is written, the register will contain the value written and no shift is performed. ATtiny2313A/4313 166 7 ...
Page 167
... USI flags as set similarly as when reading the USIDR register. The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has been completed. 8246B–AVR–09/ MSB ATtiny2313A/4313 LSB USIBR 167 ...
Page 168
... If not stibilized, the first conversion may give a wrong value. See “Internal Voltage Reference” on page 42. • Bit 5 – ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay clock cycles. ATtiny2313A/4313 168 Figure 17-1. BANDGAP ACBG ...
Page 169
... ACIS1/ACIS0 Settings ACIS0 Interrupt Mode 0 Comparator Interrupt on Output Toggle. 1 Reserved 0 Comparator Interrupt on Falling Output Edge. 1 Comparator Interrupt on Rising Output Edge – – – – ATtiny2313A/4313 – – AIN1D AIN0D DIDR R R R/W R 169 ...
Page 170
... Figure 18-1 connector. The system clock is not affected by debugWIRE and will always be the clock source selected by the CKSEL Fuses. Figure 18-1. The debugWIRE Setup ATtiny2313A/4313 170 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator dW dW(RESET) GND 1 ...
Page 171
... A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. 8246B–AVR–09/11 will not work. CC ® will insert a BREAK instruction in the Program memory. The instruc- ATtiny2313A/4313 171 ...
Page 172
... DWDR – debugWire Data Register Bit Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. This register is only accessible by the debugWIRE and can therefore not be used as a general purpose register in the normal operations. ATtiny2313A/4313 172 ...
Page 173
... Addressing the Flash During Self-Programming The Z-pointer is used to address the SPM commands. Bit ZH (R31) ZL (R30) 8246B–AVR–09/ Z15 Z14 Z13 Z12 ATtiny2313A/4313 “Lock Bits” on page Z11 Z10 173 ...
Page 174
... ZPCMSB PCWORD PAGEMSB ZPAGEMSB Note that the Page Erase and Page Write operations are addressed independently. Therefore major importance that the software addresses the same page in both the Page Erase and Page Write operation. ATtiny2313A/4313 174 Figure 19-1, below. BIT 15 ZPCMSB ...
Page 175
... Execute an SPM instruction within four clock cycles after writing SPMCSR The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to zero during this operation. The CPU is halted during the Page Write operation. 8246B–AVR–09/11 ATtiny2313A/4313 175 ...
Page 176
... Program memory operations. Bit 0x37 (0x57) Read/Write Initial Value • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and always read as zero. ATtiny2313A/4313 176 , the Flash program can be corrupted because the supply voltage is CC Table 19-2 ...
Page 177
... Writing any other combination than “100001”, “010001”, “001001”, “000101”, “000011” or “000001” in the lower six bits will have no effect. 8246B–AVR–09/11 “Device Signature Imprint Table” on page 180 “SPMCSR Can Not Be Written When EEPROM is Programmed” on page 176 ATtiny2313A/4313 for 177 ...
Page 178
... Lock bits can be erased to “1” with the Chip Erase command, only. The ATtiny2313A/4313 has no separate boot loader section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”), otherwise it is disabled. ...
Page 179
... The fuse bit can be unprogrammed using the parallel programming algorithm (see 2. This setting does not preserve EEPROM. 3. This fuse bit is not accessible in serial programming mode. 4. This setting enables SPI programming. ATtiny2313A/4313 20-4, and Table 20-5. Note that programmed fuses See ...
Page 180
... Byte addresses are used when the device itself reads the data with the LPM command. External programming devices must use word addresses. Table 20-6. Word Address 0x00 0x01 0x02 Notes: ATtiny2313A/4313 180 Low Fuse Byte Bit Name Use CKDIV8 Divides clock by 8 CKOUT ...
Page 181
... Calibration Byte The signature area of the ATtiny2313A/4313 contains two bytes of calibration data for the inter- nal oscillator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 8.0 MHz operation. During reset, this byte is automatically written into the OSCCAL regis- ter to ensure correct frequency of the oscillator ...
Page 182
... Device Signature Imprint Table Read To read the contents of the device signature imprint table, follow the below procedure: 1. Load the Z-pointer with the table index. 2. Set RSIG and SPMEN bits in SPMCSR. 3. Issue an LPM instruction within three clock cycles. ATtiny2313A/4313 182 – ...
Page 183
... Uses Z-pointer as table index ldi ZH, 0 ldi ZL Preload SPMCSR bits into R16, then write to SPMCSR ldi r16, (1<<RSIG)|(1<<SPMEN) out SPMCSR, r16 ; Issue LPM. Table data will be returned into r17 lpm r17, Z ret See “Code Examples” on page 7. ATtiny2313A/4313 “Device Signa- 183 ...
Page 184
... External Programming This section describes how to program and verify Flash memory, EEPROM, lock bits, and fuse bits in ATtiny2313A/4313. 21.1 Memory Parametrics Flash memory parametrics are summarised in Table 21-1. Device ATtiny2313A ATtiny4313 Note: EEPROM parametrics are summarised in Table 21-2. Device ATtiny2313A ATtiny4313 Note: 21.2 Parallel Programming Parallel programming signals and connections are illustrated in Figure 21-1 ...
Page 185
... XA1 and XA0 Coding XA0 Action when CLKI is Pulsed 0 Load Flash or EEPROM address (high or low address byte, determined by BS1) 1 Load data (high or low data byte for Flash, determined by BS1) 0 Load command 1 No action, idle ATtiny2313A/4313 nd high byte). Value Table 185 ...
Page 186
... Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has been applied to ensure the Prog_enable Signature has been latched. 5. Wait until V commands. 6. Exit Programming mode by power the device down or by bringing RESET pin to 0V. ATtiny2313A/4313 186 Table 21-6. Command Byte Bit Coding ...
Page 187
... Set XA1, XA0 to “00”. This enables address loading. 2. Set BS1 to “0”. This selects low address. 3. Set DATA = Address low byte (0x00 - 0xFF). 4. Give XTAL1 a positive pulse. This loads the address low byte. C. Load Data Low Byte 8246B–AVR–09/11 ATtiny2313A/4313 Table 21-1 on page 184. When programming the 187 ...
Page 188
... Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Flash page addressing is illustrated in 19-1 on page 174 ATtiny2313A/4313 188 Figure 21-3 on page 189 Figure 21-2, below. Symbols used are described in ...
Page 189
... ADDR. LOW DATA LOW DATA HIGH XX DATA XA1 XA0 BS1 XTAL1 WR OE PAGEL BS2 “Programming the Flash” on page 187 ATtiny2313A/4313 PAGEMSB PCWORD WORD ADDRESS WITHIN A PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Figure 21-3, where XX means “don’t care” and ...
Page 190
... Set OE to “1”. 21.2.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (see page 187 • A: Load Command “0000 0011”. • G: Load Address High Byte (0x00 - 0xFF). ATtiny2313A/4313 190 RDY/BSY goes low. 4 for signal waveforms ...
Page 191
... ATtiny2313A/4313 “Programming the Flash” on “Programming the Flash” on “Programming the Figure 21-5, where XX means “don’t care” and ...
Page 192
... Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at DATA (“0” means programmed). • Set OE to “1”. Fuse and lock bit mapping is illustrated in ATtiny2313A/4313 192 Write Fuse Low byte A ...
Page 193
... BS2 0 Lock Bits 1 BS2 for details on command and address loading): for details on command and address loading): Table 21-7 on page 195. ATtiny2313A/4313 0 DATA 1 BS1 “Programming the Flash” on “Programming the Flash” on Figure 21-7, below. The pin map- 193 ...
Page 194
... Depending on CKSEL fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: • Minimum low period of serial clock: – When f – When f • Minimum high period of serial clock: – When f – When f ATtiny2313A/4313 194 MOSI MISO SCK XTAL1 RESET GND If the device is clocked by the internal oscillator there is no need to connect a clock source to the CLKI pin ...
Page 195
... Table 21-7. 21.3.2 Programming Algorithm When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked on the falling edge of SCK. See Figure 22-6 on page 205 To program and verify the ATtiny2313A/4313 in the serial programming mode, the following ...
Page 196
... Load EEPROM Memory 1100 0001 Page (page access) ATtiny2313A/4313 196 supplying the address and data together with the Write instruction. EEPROM memory locations are automatically erased before new data is written. If polling (RDY/BSY) is not used, the user must wait at least t ...
Page 197
... Table Minimum Wait Delay Before Writing the Next Flash or EEPROM Location ATtiny2313A/4313 Byte4 Operation Write EEPROM page at address b. Read Lock bits. “0” = programmed, “1” = unprogrammed. See Table 20-1 on page 178 for details. Write Lock bits. Set bits = “ ...
Page 198
... Output Low Voltage V OL (5) (Except Reset Pin) (4) Output High-voltage V OH (5) (Except Reset Pin) Input Leakage I IL Current I/O Pin Input Leakage I IH Current I/O Pin R Reset Pull-up Resistor RST R I/O Pin Pull-up Resistor pu ATtiny2313A/4313 198 *NOTICE: +0.5V CC Condition Min 1.8V - 2. 2. 1.8V - 2.4V 0. 2.4V - 5.5V 0. 1.8V - 5.5V -0 ...
Page 199
... CC (7) Idle 1MHz (7) Idle 4MHz (7) Idle 8MHz (8) WDT enabled (8) WDT disabled Figure 23-29 “Minimizing Power Consumption” on page ATtiny2313A/4313 Typ. Max. 0.2 0.55 1.3 2.5 3.9 7 0.03 0.15 0.25 0 < 3V) under steady state 5V ...
Page 200
... Calibration Accuracy of Internal RC Oscillator Calibration Method Target Frequency Factory 4.0 / 8.0MHz Calibration Fixed frequency within: User 3.1 – 4.7 MHz / Calibration 7.3 – 9.1MHz Notes: ATtiny2313A/4313 200 Figure 22- MHz 1.8V 2. Fixed voltage within: 1.8V – 5.5V 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage). ...