ATUC64L4U Atmel Corporation, ATUC64L4U Datasheet - Page 206

• Manufacturer Part Number: ATUC64L4U
• Manufacturer: Atmel Corporation

Specifications of ATUC64L4U

• Flash (kbytes): 64 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 50 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: Yes
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 460
• Analog Comparators: 8
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.62 to 3.6
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 35
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

206
AVR32
LSR – Logical Shift Right
Architecture revision:
Architecture revision1 and higher.
Description
Shifts all bits in a register the amount specified to the right. The shift amount may be specified by
a register or an immediate. Zeros are shifted into the MSB.
Operation:
I.
II.
III.
Syntax:
I.
II.
III.
Operands:
I.
II.
III.
Status Flags:
Rd ← LSR(Rx, Ry[4:0]);
Rd ← LSR(Rd, sa5);
Rd ← LSR(Rs, sa5);
lsr
lsr
lsr
{d, x, y} ∈ {0, 1, …, 15}
d ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
{d,s} ∈ {0, 1, …, 15}
sa ∈ {0, 1, …, 31}
Format I: Shamt = Ry[4:0], Op = Rx
Format II: Shamt = sa5, Op = Rd
Format III: Shamt = sa5, Op = Rs
Q:
V:
N:
Z:
C:
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
if Shamt != 0
else
Rd, Rx, Ry
Rd, sa
Rd, Rs, sa
C ← Op[Shamt-1]
C ← 0
32000D–04/2011