ATxmega32A4U Atmel Corporation, ATxmega32A4U Datasheet - Page 226

• Manufacturer Part Number: ATxmega32A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega32A4U

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

19.3.3
19.3.4
19.3.5
8331A–AVR–07/11
INTCTRL – Interrupt Control Register
INTFLAGS – Interrupt Flag Register
CNT0 – Counter Register 0
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2 – COMPINTLVL[1:0]: Compare Match Interrupt Level
These bits enable the RTC32 compare match interrupt and select the interrupt level, as
described in
enabled interrupt will trigger when COMPIF in the INTFLAGS register is set.
• Bit 1:0 – OVFINTLVL[1:0]: Overflow Interrupt Level
These bits enable the RTC32 overflow interrupt and select the interrupt level, as described in
”Interrupts and Programmable Multilevel Interrupt Controller” on page
will trigger when OVFIF in the INTFLAGS register is set.
• Bit 7:2 – Reserved
These bits are reserved and will always be read as zero.
• Bit 1 – COMPIF: Compare Match Interrupt Flag
This flag is set on the next count after a compare match condition occurs. The flag is cleared
automatically when the RTC32 compare match interrupt vector is executed. The flag can also be
cleared by writing a one to its bit location.
• Bit 0 – OVFIF: Overflow Interrupt Flag
This flag is set on the next count after an overflow condition occurs. The flag is cleared automat-
ically when the RTC32 overflow interrupt vector is executed. The flag can also be cleared by
writing a one to its bit location.
The CNT0, CNT1, CNT2, and CNT3 registers represent the 32-bit value, CNT. CNT counts pos-
itive clock edges on the RTC32 clock.
Synchronization of a new CNT value to the RTC32 domain is triggered by writing CNT3. The
synchronization time is up to 12 peripheral clock cycles from updating the register until this has
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Reset Value
”Interrupts and Programmable Multilevel Interrupt Controller” on page
R
R
7
0
7
0
–
–
R
6
–
0
R
6
–
0
R
5
–
0
R
5
0
–
R
4
–
0
R
4
–
0
R
3
–
0
R/W
COMPINTLVL[1:0]
3
0
R
2
–
0
Atmel AVR XMEGA AU
R/W
2
0
COMPIF
R/W
1
0
R/W
1
0
OCINTLVL[1:0]
132. The enabled interrupt
OVFIF
R/W
0
0
R/W
0
0
INTFLAGS
132. The
INTCTRL
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