ATxmega32D4 Atmel Corporation, ATxmega32D4 Datasheet - Page 23

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ATxmega32D4

Manufacturer Part Number
ATxmega32D4
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega32D4

Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Usb Speed
No
Usb Interface
No
Spi
4
Twi (i2c)
2
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
12
Adc Speed (ksps)
200
Analog Comparators
2
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
14
Input Capture Channels
14
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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4.12.2
4.12.3
4.12.4
4.12.5
8210B–AVR–04/10
ADDR1 - Non-Volatile Memory Address Register 1
ADDR0 - Non-Volatile Memory Address Register 0
DATA2 - Non-Volatile Memory Data Register Byte 2
DATA1 - Non-Volatile Memory Data Register 1
• Bit 7:0 - ADDR[15:8]: NVM Address Register Byte 1
This register gives the address high byte when accessing either of the memory locations.
• Bit 7:0 - ADDR[7:0]: NVM Address Register Byte 0
This register gives the address low byte when accessing either of the memory locations.
The DATA2, DATA1 and ADDR0 registers represents the 24-bit value DATA.
• Bit 7:0 - DATA[23:16]: NVM Data Register 2
This register gives the data value byte 2 when running CRC check on application section, boot
section or combined.
• Bit 7:0 - DATA[15:8]: NVM Data Register Byte 1
This register gives the data value byte 1 when accessing application and boot section.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x05
Read/Write
Initial Value
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
DATA[23:16]
ADDR[15:8]
DATA[15:8]
ADDR[7:0]
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
XMEGA D
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
ADDR1
ADDR0
DATA2
DATA1
23

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