M55800A Atmel Corporation, M55800A Datasheet - Page 221

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

B.1
B.1.1
ARM DDI 0029G
Scan chains and JTAG interface
Scan chain implementation
There are three JTAG-style scan chains within the ARM7TDMI core. These enable
debugging and configuration of EmbeddedICE Logic.
A JTAG style Test Access Port (TAP) controller controls the scan chains. For further
details of the JTAG specification, refer to IEEE Standard 1149.1 - 1990 Standard Test
Access Port and Boundary-Scan Architecture.
In addition, support is provided for an optional fourth scan chain. This is intended to be
used for an external boundary-scan chain around the pads of a packaged device. The
control signals provided for this scan chain are described in Scan chain 3 on page B-20.
The scan cells are not fully JTAG compliant.
The following sections describe:
•
•
The three scan paths are referred to as:
1.
2.
3.
The scan chains are shown in Figure B-1 on page B-4.
Scan chain implementation on page B-3
TAP state machine on page B-5.
Scan chain 0 on page B-4
Scan chain 1 on page B-4
Scan chain 2 on page B-4.
Note
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Debug in Depth
B-3