SAM3N1A Atmel Corporation, SAM3N1A Datasheet - Page 51

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SAM3N1A

Manufacturer Part Number
SAM3N1A
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM3N1A

Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
48 MHz
Cpu
Cortex-M3
# Of Touch Channels
17
Hardware Qtouch Acquisition
No
Max I/o Pins
34
Ext Interrupts
34
Quadrature Decoder Channels
2
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
2
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
3
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
10.4.3.14
• BASEPRI
Priority mask bits:
0x0000 = no effect
Nonzero = defines the base priority for exception processing.
The processor does not process any exception with a priority value greater than or equal to BASEPRI.
This field is similar to the priority fields in the interrupt priority registers. The processor implements only bits[7:4] of this field,
bits[3:0] read as zero and ignore writes. See
that higher priority field values correspond to lower exception priorities.
11011A–ATARM–04-Oct-10
31
23
15
7
Base Priority Mask Register
30
22
14
6
The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is
set to a nonzero value, it prevents the activation of all exceptions with same or lower priority
level as the BASEPRI value. See the register summary in
butes. The bit assignments are:
29
21
13
5
“Interrupt Priority Registers” on page 158
28
20
12
4
Reserved
Reserved
Reserved
BASEPRI
27
19
11
3
26
18
10
2
Table 10-2 on page 44
for more information. Remember
25
17
9
1
SAM3N
for its attri-
24
16
8
0
51

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