SAM3N1B Atmel Corporation, SAM3N1B Datasheet - Page 206

• Manufacturer Part Number: SAM3N1B
• Manufacturer: Atmel Corporation

Specifications of SAM3N1B

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 17
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 10
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

11.5.6
11.5.6.1
206
SAM3N
ITM (Instrumentation Trace Macrocell)
How to Configure the ITM
The DWT contains counters for the items that follow:
The ITM is an application driven trace source that supports printf style debugging to trace Oper-
ating System (OS) and application events, and emits diagnostic system information. The ITM
emits trace information as packets which can be generated by three different sources with sev-
eral priority levels:
The following example describes how to output trace data in asynchronous trace mode.
• Watchpoint event to halt core
• Clock cycle (CYCCNT)
• Folded instructions
• Load Store Unit (LSU) operations
• Sleep Cycles
• CPI (all instruction cycles except for the first cycle)
• Interrupt overhead
• Software trace: Software can write directly to ITM stimulus registers. This can be done
• Hardware trace: The ITM emits packets generated by the DWT.
• Time stamping: Timestamps are emitted relative to packets. The ITM contains a 21-bit
• Configure the TPIU for asynchronous trace mode (refer to
• Enable the write accesses into the ITM registers by writing “0xC5ACCE55” into the
• Write 0x00010015 into the Trace Control Register:
• Write 0x1 into the Trace Enable Register:
• Write 0x1 into the Trace Privilege Register:
• Write into the Stimulus port 0 register: TPIU (Trace Port Interface Unit)
thanks to the “printf” function. For more information, refer to
Configure the
counter to generate the timestamp.
Configure the
Lock Access Register (Address: 0xE0000FB0)
The TPIU acts as a bridge between the on-chip trace data and the Instruction Trace Macro-
cell (ITM).
The TPIU formats and transmits trace data off-chip at frequencies asynchronous to the core.
– Enable ITM
– Enable Synchronization packets
– Enable SWO behavior
– Fix the ATB ID to 1
– Enable the Stimulus port 0
– Stimulus port 0 only accessed in privileged mode (Clearing a bit in this register will
result in the corresponding stimulus port being accessible in user mode.)
ITM”.
TPIU”)
Section 11.5.6.3 “5.4.3. How to
Section 11.5.6.1 “How to
11011A–ATARM–04-Oct-10