SAM3N4A Atmel Corporation, SAM3N4A Datasheet - Page 509

• Manufacturer Part Number: SAM3N4A
• Manufacturer: Atmel Corporation

Specifications of SAM3N4A

• Flash (kbytes): 256 Kbytes
• Pin Count: 48
• Max. Operating Frequency: 48 MHz
• Cpu: Cortex-M3
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 79
• Ext Interrupts: 79
• Quadrature Decoder Channels: 2
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 2
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 24
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.62 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 29-5. Receiver Ready
29.5.2.4
Figure 29-6. Receiver Overrun
29.5.2.5
Figure 29-7. Parity Error
29.5.2.6
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
RXRDY
URXD
RXRDY
OVRE
URXD
RXRDY
URXD
PARE
S
S
Receiver Overrun
Parity Error
Receiver Framing Error
D0
D0
S
D1
D1
D0
D2
D2
If UART_RHR has not been read by the software (or the Peripheral Data Controller or DMA
Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the
OVRE status bit in UART_SR is set. OVRE is cleared when the software writes the control regis-
ter UART_CR with the bit RSTSTA (Reset Status) at 1.
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in UART_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in UART_SR is set at the same time the RXRDY is set.
The parity bit is cleared when the control register UART_CR is written with the bit RSTSTA
(Reset Status) at 1. If a new character is received before the reset status command is written,
the PARE bit remains at 1.
When a start bit is detected, it generates a character reception when all the data bits have been
sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error)
bit in UART_SR is set at the same time the RXRDY bit is set. The FRAME bit remains high until
the control register UART_CR is written with the bit RSTSTA at 1.
D1
D3
D3
D2
D4
D4
D3
D5
D5
D4
D6
D6
D5
D7
D7
D6
P
Wrong Parity Bit
P
D7
stop
P
S
S
stop
D0
Read UART_RHR
D0
D1
D1
D2
D2
D3
RSTSTA
D3
D4
D4
D5
D5
D6
D6
D7
D7
P
SAM3N
SAM3N
P
stop
RSTSTA
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