SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 140

• Manufacturer Part Number: SAM7S256
• Manufacturer: Atmel Corporation

Specifications of SAM7S256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Debug Interface
5-18
Sending a message to the debugger
When the processor has to send a message to the debugger, it must check that the
communications data write register is free for use by finding out if the W bit of the
debug communications control register is clear.
The processor reads the DCC control register to check status of the bit 1:
If the W bit is clear then the communications data write register is clear.
•
As the data transfer occurs from the processor to the DCC data write register, the W bit
is set in the DCC control register. When the debugger polls this register it sees a
synchronized version of both the R and W bit. When the debugger sees that the W bit
is set, it can read the DCC data write register and scan the data out. The action of reading
this data register clears the W bit of the DCC control register. At this point, the
communications process can begin again.
Receiving a message from the debugger
Transferring a message from the debugger to the processor is similar to sending a
message to the debugger. In this case, the debugger polls the R bit of the DCC control
register:
•
•
When the DCC data read register is free, data is written there using the JTAG interface.
The action of this write sets the R bit in the DCC control register.
The processor polls the DCC control register. If the R bit is set, there is data that can be
read using an MRC instruction to coprocessor 14. The action of this load clears the R
bit in the DCC control register. When the debugger polls this register and sees that the
R bit is clear, the data has been taken and the process can now be repeated.
Interrupt driven use of the DCC
An alternative, and potentially more efficient, method to polling the debug
communications control register is to use the COMMTX and COMMRX outputs from
the ARM7TDMI processor. You can use these outputs to interrupt the processor when:
•
If the W bit is set, previously written data has not been read by the debugger. The
processor must continue to poll the control register until the W bit is clear.
if the R bit is clear, the DCC data read register is free and data can be placed there
for the processor to read
if the R bit is set, previously deposited data has not yet been collected, so the
debugger must wait.
a word is available to be read from the DCC data read register
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ARM DDI 0029G