SAM7S256 Atmel Corporation, SAM7S256 Datasheet - Page 160

• Manufacturer Part Number: SAM7S256
• Manufacturer: Atmel Corporation

Specifications of SAM7S256

• Flash (kbytes): 256 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 32
• Ext Interrupts: 32
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 3
• Ssc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Instruction Cycle Timings
6.11
6-18
Data swap
Cycle
1
2
3
4
This is similar to the load and store register instructions, but the actual swap takes place
in the second and third cycles. In the second cycle, the data is fetched from external
memory. In the third cycle, the contents of the source register are written out to the
external memory. The data read in the second cycle is written into the destination
register during the fourth cycle.
LOCK is driven HIGH during the second and third cycles to indicate that both cycles
must be allowed to complete without interruption.
The data swapped can be a byte or word quantity. Halfword quantities cannot be
specified.
The swap operation can be aborted in either the read or write cycle, and in both cases
the destination register is not affected.
The cycle timings are listed in Table 6-14 where:
•
The data swap operation is not available in Thumb state.
s represents the size of the data transfer shown by MAS[1:0] (see Table 6-10 on
page 6-13), s can only represent byte and word transfers. Halfword transfers are
not available.
Address
pc+8
Rn
Rn
pc+12
pc+12
Note
Copyright © 1994-2001. All rights reserved.
MAS [1:0]
2
b/w
b/w
2
nRW
0
0
1
0
Table 6-14 Data swap instruction cycle operations
Data
(Rn)
-
(pc+8)
Rm
nMREQ
0
0
1
0
SEQ
0
0
0
1
nOPC
0
1
1
1
ARM DDI 0029G
LOCK
0
1
1
0