SAM7X128 Atmel Corporation, SAM7X128 Datasheet - Page 129

• Manufacturer Part Number: SAM7X128
• Manufacturer: Atmel Corporation

Specifications of SAM7X128

• Flash (kbytes): 128 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Entry into debug state on breakpoint
The ARM7TDMI core marks instructions as being breakpointed as they enter the
instruction pipeline, but the core does not enter debug state until the instruction reaches
the Execute stage.
Breakpointed instructions are not executed. Instead, the processor enters debug state.
When you examine the internal state, you see the state before the breakpointed
instruction. When your examination is complete, remove the breakpoint. This is usually
handled automatically by the debugger which also restarts program execution from the
previously-breakpointed instruction.
When a breakpointed conditional instruction reaches the Execute stage of the pipeline,
the breakpoint is always taken.
The processor enters debug state regardless of whether the condition is met.
A breakpointed instruction does not cause the ARM7TDMI core to enter debug state
when:
•
BREAKPT
A branch or a write to the PC precedes the breakpointed instruction. In this case,
when the branch is executed, the core flushes the instruction pipeline and so
cancels the breakpoint.
DBGACK
Note
nMREQ
D[31:0]
A[31:0]
MCLK
SEQ
Copyright © 1994-2001. All rights reserved.
Memory cycles
Figure 5-3 Debug state entry
Internal cycles
Debug Interface
5-7