SAM7X256 Atmel Corporation, SAM7X256 Datasheet - Page 186

• Manufacturer Part Number: SAM7X256
• Manufacturer: Atmel Corporation

Specifications of SAM7X256

• Flash (kbytes): 256 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 55 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 62
• Ext Interrupts: 62
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 3
• Can: 1
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 64
• Self Program Memory: NO
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

AC and DC Parameters
7.11
7-14
Coprocessor timing
Figure 7-10 shows the ARM7TDMI processor coprocessor timing. The timing
parameters used in Figure 7-10 are listed in Table 7-10.
In Figure 7-10, usually nMREQ and SEQ become valid T
MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the
instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ
depends on T
2, and so the timing of nMREQ and SEQ is always T
nMREQ
MCLK
nCPI
SEQ
CPA
CPB
Note
Copyright © 1994-2001. All rights reserved.
cpms
. Most systems can generate CPA and CPB during the previous phase
Symbol
T
T
T
T
T
cph
cpi
cpih
cpms
cps
Phase 1
T
cpi
Parameter
CPA,CPB hold time from MCLKr
MCLKf to nCPI valid
nCPI hold time from MCLKf
CPA, CPB to nMREQ, SEQ
CPA, CPB setup to MCLKr
T
cpms
T
cps
Table 7-10 Coprocessor timing parameters
T
cph
Phase 2
Figure 7-10 Coprocessor timing
msd
.
T
msd
cpih
after the falling edge of
Parameter type
Minimum
Maximum
Minimum
Maximum
Minimum
ARM DDI 0029G