SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 186

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.4
22.5
186
Block Diagram
Processor Clock Controller
SAM9G35
Figure 22-2. General Clock Block Diagram
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation.
Refer to the Atmel application note,
Systems, lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
PLLACK
/1,/2
UPLLCK
MAINCK
SLCK
USBS
Master Clock Controller
/1,/2,/3,/4,...,/64
Prescaler
MAINCK
UPLLCK
USBDIV+1
SLCK
Optimizing Power Consumption for AT91SAM9261-based
Programmable Clock Controller
/1 /2 /3 /4
X /1 /1.5 /2
/4
Divider
/1,/2,/4,...,/64
Prescaler
UHP12M
UHP48M
ON/OFF
OHCI
USB
USB
EHCI
Clock Controller
Processor
Controller
Peripherals
Clock
ON/OFF
/2
Divider
pck[..]
11053B–ATARM–22-Sep-11
PCK
int
DDRCK
2x MCK
MCK
Periph_clk[..]