SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 226

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

23.5.4
23.5.5
23.5.6
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226
SAM9G35
SAM9G35
Output Control
Synchronous Data Output
Multi Drive Control (Open Drain)
Note that multiplexing of peripheral lines A, B, C and D only affects the output line. The periph-
eral input lines are always connected to the pin input.
After reset, PIO_ABCDSR1 and PIO_ABCDSR2 are 0, thus indicating that all the PIO lines are
configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO
Controller resets in I/O line mode.
Writing in PIO_ABCDSR1 and PIO_ABCDSR2 manages the multiplexing regardless of the con-
figuration of the pin. However, assignment of a pin to a peripheral function requires a write in the
peripheral selection registers (PIO_ABCDSR1 and PIO_ABCDSR2) in addition to a write in
PIO_PDR.
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at
0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B or C or D depending
on the value in PIO_ABCDSR1 and PIO_ABCDSR2 (ABCD Select Registers) determines
whether the pin is driven or not.
When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This
is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register).
The results of these write operations are detected in PIO_OSR (Output Status Register). When
a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at
1, the corresponding I/O line is driven by the PIO controller.
The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data
Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set
and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O
lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to
be controlled by the PIO controller or assigned to a peripheral function. This enables configura-
tion of the I/O line prior to setting it to be managed by the PIO Controller.
Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it
defines the first level driven on the I/O line.
Clearing one (or more) PIO line(s) and setting another one (or more) PIO line(s) synchronously
cannot be done by using PIO_SODR and PIO_CODR registers. It requires two successive write
operations into two different registers. To overcome this, the PIO Controller offers a direct con-
trol of PIO outputs by single write access to PIO_ODSR (Output Data Status Register).Only bits
unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in
PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by
writing to PIO_OWDR (Output Write Disable Register).
After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at
0x0.
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This
feature permits several drivers to be connected on the I/O line which is driven low only by each
device. An external pull-up resistor (or enabling of the internal one) is generally required to guar-
antee a high level on the line.
• the corresponding bit at level 1 in PIO_ABCDSR1 and the corresponding bit at level 1 in
PIO_ABCDSR2 means peripheral D is selected.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11