SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 112

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Coprocessor Interface
4.4.4
4-8
Decode stage
Fetch stage
Execute
D[31:0]
Consequences of busy-waiting
MCLK
stage
nCPI
CPA
CPB
ADD
Instr fetch
(ADD)
CPA and CPB are ignored by the ARM7TDMI processor when it does not have a
undefined or coprocessor instruction in the Execute stage of the pipeline.
A summary of coprocessor signaling is listed in Table 4-3 on page 4-7.
A busy-waited coprocessor instruction can be interrupted. If a valid FIQ or IRQ occurs
and the appropriate bit is clear in the CSPR, then the ARM7TDMI processor abandons
the coprocessor instruction, and signals this by taking nCPI HIGH. A coprocessor that
is capable of busy-waiting must monitor nCPI to detect this condition. When the
ARM7TDMI core abandons a coprocessor instruction, the coprocessor also abandons
the instruction, and continues tracking the ARM7TDMI processor pipeline.
ADD
SUB
Instr fetch
(SUB)
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CDP
SUB
ADD
Instr fetch
(CDP)
CDP
TST
SUB
Instr fetch
(TST)
Instr fetch
(SUB)
Coprocessor
busy waiting
Figure 4-1 Coprocessor busy-wait sequence
CDP
SUB
TST
SUB
TST
Instr fetch
ARM DDI 0029G
SUB
Instr fetch