SAM9M11 Atmel Corporation, SAM9M11 Datasheet - Page 217

• Manufacturer Part Number: SAM9M11
• Manufacturer: Atmel Corporation

Specifications of SAM9M11

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: Yes
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Dac Resolution (bits): No
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No / Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

ARM DDI 0029G
Name
TAPSM[3:0]
TAP controller
state machine
TBE
Test bus enable
TBIT
TCK
TCK1
TCK, phase one
TCK2
TCK, phase two
TDI
TDO
Test data output
TMS
VDD
Power supply
VSS
Ground
Copyright © 1994-2001. All rights reserved.
Type
O4
IC
O4
IC
O4
O4
IC
O4
IC
P
P
Description
These reflect the current state of the TAP controller state machine. These
bits change on the rising edge of TCK.
See Figure B-2 on page B-5.
When LOW, D[31:0], A[31:0], LOCK, MAS[1:0], nRW, nTRANS,
and nOPC are set to high impedance.
Similar in effect as if both ABE and DBE had been driven LOW.
However, TBE does not have an associated scan cell and so allows
external signals to be driven high impedance during scan testing.
Under normal operating conditions TBE must be HIGH.
When the processor is executing the THUMB instruction set, this is
HIGH. It is LOW when executing the ARM instruction set.
This signal changes in phase two in the first execute cycle of a BX
instruction.
Clock signal for all test circuitry. When in debug state, this is used to
generate DCLK, TCK1, and TCK2.
HIGH when TCK is HIGH (slight phase lag due to the internal clock
non-overlap).
HIGH when TCK is LOW (slight phase lag due to the internal clock
non-overlap).
It is the non-overlapping complement of TCK1.
Serial data for the scan chains.
Serial data from the scan chains.
Mode select for scan chains.
Provide power to the device.
These connections are the ground reference for all signals.
Table A-3 Signal Descriptions (continued)
Signal Description
A-11