AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 128

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

128
Atmel ATtiny24/44/84 [Preliminary]
Figure 16-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
ing steps:
1. The start condition is generated by the Master by forcing the SDA line low while the
2. In addition, the start detector will hold the SCL line low after the master has forced a
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
4. After eight bits containing the slave address and data direction (read or write) are
5. If the slave is addressed, it holds the SDA line low during the acknowledgment cycle
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
If the slave is not able to receive more data, it does not acknowledge the data byte it has last
received. When the master does a read operation, it must terminate the operation by forcing
the acknowledge bit low after the last byte is transmitted.
Figure 16-6. Start Condition Detector, Logic Diagram
SCL line is high (A). SDA can be forced low either by writing a logical zero to bit 7 of the
shift register, or by setting the corresponding bit in the PORT register to zero. Note that
the data direction register bit must be set to one for the output to be enabled. The slave
device's start detector logic
sets the USISIF Flag. The flag can generate an interrupt if necessary.
negative edge on this line (B). This allows the slave to wake up from sleep or complete
its other tasks before setting up the shift register to receive the address. This is done by
clearing the start condition flag and resetting the counter.
samples the data and shift it into the Serial Register at the positive edge of the SCL
clock.
transferred, the slave counter overflows and the SCL line is forced low (D). If the slave
is not the one the master has addressed, it releases the SCL line and waits for a new
start condition.
before holding the SCL line low again (i.e., the counter register must be set to 14
before releasing SCL at (D)). Depending on the state of the R/W bit, the master or
slave enables its output. If the bit is set, a master read operation is in progress (i.e., the
slave drives the SDA line). The slave can hold the SCL line low after the acknowledge-
ment cycle (E).
given by the master (F), or a new start condition is given.
SDA
SCL
Write( USISIF)
A B
S
C
ADDRESS
SDA
SCL
1 - 7
R/W
(Figure 16-5 on page
(Figure 16-6 on page
8
D
ACK
9
E
DATA
1 - 8
D Q
CLR
128) detects the start condition and
128), a bus transfer involves the follow-
ACK
9
D Q
CLR
DATA
1 - 8
USISIF
CLOCK
HOLD
ACK
9
7701E–AVR–02/11
P
F