AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 74

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

13.5
74
Output Compare Unit
Atmel ATtiny24/44/84 [Preliminary]
Signal description (internal signals):
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clk
source, selected by the Clock Select bits (CS02:0). When no clock source is selected
(CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU,
regardless of whether clk
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located
in the timer/counter control register A (TCCR0A) and the WGM02 bit located in the timer/coun-
ter control register B (TCCR0B). There are close connections between how the counter
behaves (counts) and how waveforms are generated on the output compare output (OC0A).
For more details about advanced counting sequences and waveform generation, see
of Operation” on page
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected
by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is
executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location. The Waveform Generator uses the match signal to generate an output according to
the operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits.
The max and bottom signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation. See
77.
Figure 13-3 on page 75
count
direction
clear
clk
top
bottom
Tn
77.
shows a block diagram of the Output Compare unit.
T0
is present or not. A CPU write overrides (has priority over) all
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T0
). clk
T0
can be generated from an external or internal clock
“Modes of Operation” on page
T0
in the following.
7701E–AVR–02/11
“Modes