SAM3N0A Atmel Corporation, SAM3N0A Datasheet - Page 552

• Manufacturer Part Number: SAM3N0A
• Manufacturer: Atmel Corporation

30.7.7.3
11011A–ATARM–04-Oct-10
11011A–ATARM–04-Oct-10
Data Transfer
Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge
(depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity
bit and no Stop bit.
The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register
(US_MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The
MSB data bit is always sent first in SPI Mode (Master or Slave).
Four combinations of polarity and phase are available for data transfers. The clock polarity is
programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the
CPHA bit. These two parameters determine the edges of the clock signal upon which data is
driven and sampled. Each of the two parameters has two possible states, resulting in four possi-
ble combinations that are incompatible with one another. Thus, a master/slave pair must use the
same parameter pair values to communicate. If multiple slaves are used and fixed in different
configurations, the master must reconfigure itself each time it needs to communicate with a dif-
ferent slave.
Table 30-14. SPI Bus Protocol Mode
SPI Bus Protocol Mode
0
1
2
3
CPOL
0
0
1
1
CPHA
1
0
1
0
SAM3N
SAM3N
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