SAM3X8C Atmel Corporation, SAM3X8C Datasheet - Page 439

• Manufacturer Part Number: SAM3X8C
• Manufacturer: Atmel Corporation

26.10 Standard Read and Write Protocols
26.10.1
Figure 26-7. Standard Read Cycle
26.10.1.1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Read Waveforms
NRD Waveform
NBS0,NBS1,
A0, A1
D[15:0]
A[23:2]
MCK
NRD
NCS
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the A address bus. NWE represents either the NWE sig-
nal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..7] chip select lines.
The read cycle is shown on
The read cycle starts with the address setting on the memory address bus, i.e.:
The NRD signal is characterized by a setup timing, a pulse width and a hold timing.
1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD
2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD
3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD
NCS_RD_SETUP
falling edge.
rising edge.
rising edge.
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
NRD_SETUP
Figure
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
26-7.
NRD_HOLD
NCS_RD_HOLD
SAM3X/A
SAM3X/A
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