SAM3X8C

Manufacturer Part NumberSAM3X8C
ManufacturerAtmel Corporation
SAM3X8C datasheets
 
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Features
Core
®
®
– ARM
Cortex
-M3 revision 2.0 running at up to 84 MHz
– Memory Protection Unit (MPU)
®
– Thumb
-2 instruction set
– 24-bit SysTick Counter
– Nested Vector Interrupt Controller
Memories
– From 256 to 512 Kbytes embedded Flash, 128-bit wide access, memory accelerator, dual bank
– From 32 to 100 Kbytes embedded SRAM with dual banks
– 16 Kbytes ROM with embedded bootloader routines (UART, USB) and IAP routines
– Static Memory Controller (SMC): SRAM, NOR, NAND support. NAND Flash
controller with 4-kbyte RAM buffer and ECC
– SDRAM Controller
System
– Embedded voltage regulator for single supply operation
– POR, BOD and Watchdog for safe reset
– Quartz or ceramic resonator oscillators: 3 to 20 MHz main and optional low power
32.768 kHz for RTC or device clock.
– High precision 8/12 MHz factory trimmed internal RC oscillator with 4 MHz Default
Frequency for fast device startup
– Slow Clock Internal RC oscillator as permanent clock for device clock in low power
mode
– One PLL for device clock and one dedicated PLL for USB 2.0 High Speed Mini
Host/Device
– Temperature Sensor
– Up to 17 peripheral DMA (PDC) channels and 6-channel central DMA plus
dedicated DMA for High-Speed USB Mini Host/Device and Ethernet MAC
Low Power Modes
– Sleep and Backup modes, down to 2.5 µA in Backup mode.
– Backup domain: VDDBU pin, RTC, eight 32-bit backup registers
– Ultra Low-power RTC
Peripherals
– USB 2.0 Device/Mini Host: 480 Mbps, 4-kbyte FIFO, up to 10 bidirectional
Endpoints, dedicated DMA
– Up to 4 USARTs (ISO7816, IrDA
and one UART
– 2 TWI (I2C compatible), up to 6 SPIs, 1 SSC (I2S), 1 HSMCI (SDIO/SD/MMC) with up
to 2 slots
– 9-Channel 32-bit Timer/Counter (TC) for capture, compare and PWM mode,
Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
– Up to 8-channel 16-bit PWM (PWMC) with Complementary Output, Fault Input, 12-
bit Dead Time Generator Counter for Motor Control
– 32-bit Real Time Timer (RTT) and RTC with calendar and alarm features
– 16-channel 12-bit 1Msps ADC with differential input mode and programmable gain
stage
– One 2-channel 12-bit 1 Msps DAC
– One Ethernet MAC 10/100 (EMAC) with dedicated DMA
– Two CAN Controller with eight Mailboxes
– One True Random Number Generator (TRNG)
I/O
– Up to 164 I/O lines with external interrupt capability (edge or level sensitivity),
debouncing, glitch filtering and on-die Series Resistor Termination
– Up to Six 32-bit Parallel Input/Outputs (PIO)
Packages
– 100-lead LQFP, 14 x 14 mm, pitch 0.5 mm
– 100-ball LFBGA, 9 x 9 mm, pitch 0.8 mm
– 144-lead LQFP, 20 x 20 mm, pitch 0.5 mm
– 144-ball LFBGA, 10 x 10 mm, pitch 0.8 mm
®
, Flow Control, SPI, Manchester and LIN support)
AT91SAM
ARM-based
Flash MCU
SAM3X
SAM3A
Series
Summary
11057AS–ATARM–10-Feb-12

SAM3X8C Summary of contents

  • Page 1

    Features • Core ® ® – ARM Cortex -M3 revision 2.0 running MHz – Memory Protection Unit (MPU) ® – Thumb -2 instruction set – 24-bit SysTick Counter – Nested Vector Interrupt Controller • Memories – ...

  • Page 2

    SAM3X/A Description Atmel’s SAM3X/A series is a member of a family of Flash microcontrollers based on the high performance 32-bit ARM Cortex-M3 RISC processor. It operates at a maximum speed of 84 MHz and features up to 512 Kbytes ...

  • Page 3

    ... USART/ UART (3) SPI HSMCI Notes: 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 Configuration Summary SAM3X8E SAM3X8C SAM3X4E 2 x 256 Kbytes 2 x 256 Kbytes 2 x 128 Kbytes Kbytes Kbytes Kbytes Kbytes Kbytes Yes - Yes (1) 4K bytes ...

  • Page 4

    SAM3X/A Block Diagram Figure 2-1. SAM3A4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD ...

  • Page 5

    Figure 2-2. SAM3X4/8C (100 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC 12M XOUT WDT RC 12/8/4 M FWUP XIN32 XOUT32 ERASE VDDBU VDDCORE VDDUTMI NRST PIOA PIOC TWCK0 TWD0 TWCK1 TWD1 URXD UTXD RXD0 TXD0 SCK0 ...

  • Page 6

    Figure 2-3. SAM3X4/8E (144 pins) Block Diagram System Controller TST PCK0-PCK2 PLLA UPLL XIN OSC XOUT WDT RC 12/8/4 M SHDN SUPC FWUP XIN32 OSC 32K XOUT32 RC 32K ERASE GPBREG NRSTB VDDBU VDDCORE RSTC VDDUTMI NRST PIOA PIOC PIOE ...

  • Page 7

    Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function VDDIO Peripherals I/O Lines Power Supply VDDUTMI USB UTMI+ Interface Power Supply VDDOUT Voltage Regulator Output Voltage Regulator, ADC and DAC Power VDDIN Supply GNDUTMI USB UTMI+ ...

  • Page 8

    Table 3-1. Signal Description List (Continued) Signal Name Function TCK/SWCLK Test Clock/Serial Wire Clock TDI Test Data In Test Data Out / Trace Asynchronous Data TDO/TRACESWO Out Test Mode Select /Serial Wire TMS/SWDIO Input/Output JTAGSEL JTAG Selection Flash and NVM ...

  • Page 9

    Table 3-1. Signal Description List (Continued) Signal Name Function PA0 - PA31 Parallel IO Controller A PB0 - PB31 Parallel IO Controller B PC0 - PC30 Parallel IO Controller C PD0 - PD30 Parallel IO Controller D PE0 - PE31 ...

  • Page 10

    Table 3-1. Signal Description List (Continued) Signal Name Function NANDOE NAND Flash Output Enable NANDWE NAND Flash Write Enable NANDRDY NAND Ready NANDCLE NAND Flash Command Line Enable NANDALE NAND Flash Address Line Enable SDCK SDRAM Clock SDCKE SDRAM Clock ...

  • Page 11

    Table 3-1. Signal Description List (Continued) Signal Name Function ECRSDV Carrier Sense and Data Valid ERX0 - ERX3 Receive Data ERXER Receive Error ECRS Carrier Sense ECOL Collision Detected EMDC Management Data Clock EMDIO Management Data Input/Output CANRXx CAN Input ...

  • Page 12

    Table 3-1. Signal Description List (Continued) Signal Name Function TWCKx TWIx Two-wire Serial Clock AD0 - AD14 Analog Inputs ADTRG ADC Trigger ADVREF ADC and DAC Reference DAC0 DAC channel 0 analog output DAC1 DAC channel 1 analog output DATRG ...

  • Page 13

    Package and Pinout 4.1 SAM3A4/8C and SAM3X4/8C Package and Pinout The SAM3A4/8C and SAM3X4/8C are available in 100-lead LQFP and 100-ball LFBGA packages. 4.1.1 100-lead LQFP Package Outline Figure 4-1. 4.1.2 100-ball LFBGA Package Outline Figure 4-2. 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 ...

  • Page 14

    LQFP Pinout Table 4-1. 100-lead LQFP SAM3A4/8C and SAM3X4/8C Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PA0 14 PA1 ...

  • Page 15

    LFBGA Pinout Table 4-2. 100-ball LFBGA SAM3X4/8E Package and Pinout A1 PB26 A2 PB24 A3 PB22 A4 PB14 A5 PC0 A6 PB9 A7 PB6 A8 PB2 A9 PA28 A10 PA26 B1 PA11 B2 PB25 B3 PB23 B4 PA10 ...

  • Page 16

    SAM3X4/8E Package and Pinout The SAM3X4/8E is available in 144-lead LQFP and 144-ball LFBGA packages. 4.2.1 144-lead LQFP Package Outline Figure 4-3. Orientation of the 144-lead LQFP Package 4.2.2 144-ball LFBGA Package Outline The 144-Ball LFBGA package has a ...

  • Page 17

    LQFP Pinout Table 4-3. 144-lead LQFP SAM3X4/8E Pinout 1 PB26 2 PA9 3 PA10 4 PA11 5 PA12 6 PA13 7 PA14 8 PA15 9 PA17 10 VDDCORE 11 VDDIO 12 GND 13 PD0 14 PD1 15 PD2 ...

  • Page 18

    LFBGA Pinout Table 4-4. 144-ball LFBGA SAM3X4/8E Pinout A1 PA9 A2 PB23 A3 PB14 A4 PC26 A5 PC24 A6 PC20 A7 PB10 A8 PB6 A9 PB4 A10 PC4 A11 PA28 A12 PA27 B1 PA10 B2 PB26 B3 PB24 ...

  • Page 19

    Power Considerations 5.1 Power Supplies The SAM3X/A series product has several types of power supply pins: • VDDCORE pins: Power the core, the embedded memories and the peripherals; voltage ranges from 1.62V to 1.95V. • VDDIO pins: Power the ...

  • Page 20

    Typical Powering Schematics The SAM3X/A series supports a 1.62V-3.6V single supply mode. The internal regulator input connected to the source and its output feeds VDDCORE. schematics. Figure 5-1. Note: SAM3X/A SAM3X Single Supply Main Supply (1.8V-3.6V) Restrictions ...

  • Page 21

    Figure 5-2. Note: 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 Core Externally Supplied Main Supply (1.62V-3.6V) VDDCORE Supply (1.62V-1.95V) Restrictions For USB, VDDUTMI needs to be greater than 3.0V. For ADC, VDDANA needs to be greater than 2.0V. For DAC, VDDANA needs to be greater ...

  • Page 22

    Note: Note: 5.4 Active Mode Active mode is the normal running mode with the core clock running from the fast RC oscillator, the main crystal oscillator or the PLLA. The power management controller can be used to adapt the frequency ...

  • Page 23

    The Supply Controller, zero-power power-on reset, RTT, RTC, Backup registers and 32 kHz Oscillator (RC or crystal oscillator selected by software in the Supply Controller) are running. The regulator and the core supply are off. Backup Mode is based on ...

  • Page 24

    The processor can be awakened from an interrupt if WFI instruction of the Cortex M3 is used, or from an event if the WFE instruction is used to enter this mode. 5.5.4 Low Power Mode Summary Table The modes detailed ...

  • Page 25

    Wake-up Sources The wake-up events allow the device to exit the backup mode. When a wake-up event is detected, the Supply Controller performs a sequence which automatically reenables the core power supply. Figure 5-3. Wake-up Source SMEN sm_int RTCEN ...

  • Page 26

    Fast Start-Up The SAM3X/A series allows the processor to restart in a few microseconds while the processor is in wait mode. A fast start up can occur upon detection of a low level on one of the 19 wake-up ...

  • Page 27

    Input/Output Lines The SAM3X/A has different kinds of input/output (I/O) lines, such as general purpose I/Os (GPIO) and system I/Os. GPIOs can have alternate functions thanks to multiplexing capabilities of the PIO controllers. The same PIO line can be ...

  • Page 28

    Table 6-1. System I/O Configuration Pin List SYSTEM_IO Default Function Bit Number Peripheral After Reset TCK/SWCLK A A TDO/TRACESWO A TMS/SWDIO Note: 6.2.1 Serial Wire JTAG Debug Port (SWJ-DP) Pins The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, ...

  • Page 29

    NRST Pin The NRST pin is bidirectional handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components, or asserted low externally to reset the microcontroller. It will ...

  • Page 30

    Processor and Architecture 7.1 ARM Cortex-M3 Processor • Version 2.0 • Thumb-2 (ISA) subset consisting of all base Thumb-2 instructions, 16-bit and 32-bit. • Harvard processor architecture enabling simultaneous instruction fetch with data load/store. • Three-stage pipeline. • Single ...

  • Page 31

    Matrix Slaves The Bus Matrix of the SAM3X/A series product manages 9 slaves. Each slave has its own arbi- ter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave ...

  • Page 32

    DMA Controller • Acting as one Matrix Master • Embeds 4 (SAM3A and 100-pin SAM3X (144-pin SAM3X) channels Table 7-4. 8 bytes FIFO for Channel Buffering 32 bytes FIFO for Channel Buffering • Linked List support with ...

  • Page 33

    Peripheral DMA Controller • Handles data transfer between peripherals and memories • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from ...

  • Page 34

    Debug and Test Features • Debug access to all memory and registers in the system, including Cortex-M3 register bank when the core is running, halted, or held in reset • Serial Wire Debug Port (SW-DP) and Serial Wire JTAG ...

  • Page 35

    Product Mapping Figure 8-1. SAM3X/A Product Mapping Code Boot Memory Internal Flash 0 Internal Flash 1 Internal ROM Reserved HALF_FLASHSIZE address: - 512ko products: 0x000C0000 - 256k products: 0x000A0000 - 128k products: 0x00090000 SRAM SRAM0 SRAM1 NFC (SRAM) UOTGHS ...

  • Page 36

    Memories 9.1 Embedded Memories 9.1.1 Internal SRAM • The 100-pin SAM3A/X8 product embeds a total of 96 Kbytes high-speed SRAM (64 Kbytes SRAM0 and 32 Kbytes SRAM1). • The 100-pin SAM3A/X4 product embeds a total of 64 Kbytes high-speed ...

  • Page 37

    The user can choose between high performance or lower current consumption by selecting either 128-bit or 64-bit access. It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the ...

  • Page 38

    The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when TST, PA0, PA1 are set to high, PA2 and PA3 ...

  • Page 39

    The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 1 is set to 0. 9.1.3.10 GPNVM Bits The SAM3X/A series features three GPNVM bits that can be cleared or set respectively through ...

  • Page 40

    External Memories The 144-pin SAM3X features one External Memory Bus to offer interface to a wide range of external memories and to any parallel peripheral. 9.2.1 External Memory Bus • Integrates Four External Memory Controllers: – Static Memory Controller ...

  • Page 41

    System Controller The System Controller is a set of peripherals, which allow handling of key elements of the sys- tem such as power, resets, clocks, time, interrupts, watchdog, etc... The System Controller User Interface also embeds the registers allowing ...

  • Page 42

    Figure 10-1. System Controller Block Diagram VDDBU FWUP SHDN NRSTB Zero-Power Power-on Reset General Purpose Backup Registers SLCK RTC SLCK RTT osc32k_xtal_en XIN32 Xtal 32 kHz Oscillator XOUT32 Embedded 32 kHz RC osc32k_rc_en Oscillator Backup Power Supply vddcore_nreset NRST FSTT0 ...

  • Page 43

    System Controller and Peripherals Mapping Please refer to All the peripherals are in the bit band region and are mapped in the bit band alias region. 10.2 Power-on-Reset, Brownout and Supply Monitor The SAM3X/A embeds three features to monitor, ...

  • Page 44

    The Slow Clock generator is based kHz crystal oscillator and an embedded 32 kHz RC oscillator. The Slow Clock defaults to the RC oscillator, but the software can enable the crystal oscillator and select it as the ...

  • Page 45

    Figure 10-2. Clock Generator Block Diagram 10.6 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock HCLK • the Free running processor clock FCLK • the Cortex SysTick ...

  • Page 46

    Figure 10-3. The SysTick calibration value is fixed at 10500, which allows the generation of a time base with SystTick clock to 10.5 MHz (max HCLK/8). 10.7 Watchdog Timer • 16-bit key-protected once-only Programmable Counter • Windowed, ...

  • Page 47

    ... Chip Identifier (CHIPID) registers permit recognition of the device and its revision. • .JTAG ID: 0x05B2B03F Table 10-1. ATSAM3X8H (Rev A) ATSAM3X8E (Rev A) ATSAM3X4E (Rev A) ATSAM3X8C (Rev A) ATSAM3X4C (Rev A) ATSAM3A8C (Rev A) ATSAM3A4C (Rev A) 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 restoration between interrupts. ...

  • Page 48

    UART • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun ...

  • Page 49

    Peripherals 11.1 Peripheral Identifiers Table 11-1 required for the control of the peripheral interrupt with the Nested Vectored Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Note that some Peripherals are always ...

  • Page 50

    Table 11-1. Peripheral Identifiers (Continued) Instance ID Instance Name 29 TC2 30 TC3 31 TC4 32 TC5 33 TC6 34 TC7 35 TC8 36 PWM 37 ADC 38 DACC 39 DMAC 40 UOTGHS 41 TRNG 42 EMAC 43 CAN0 44 ...

  • Page 51

    PIO Controller A Multiplexing Table 11-2. Multiplexing on PIO Controller A (PIOA) I/O Line Peripheral A PA0 CANTX0 PA1 CANRX0 PA2 TIOA1 PA3 TIOB1 PA4 TCLK1 PA5 TIOA2 PA6 TIOB2 PA7 TCLK2 PA8 URXD PA9 UTXD PA10 RXD0 PA11 ...

  • Page 52

    PIO Controller B Multiplexing Table 11-3. Multiplexing on PIO Controller B (PIOB) I/O Line Peripheral A (1) PB0 ETXCK/EREFCK (1) PB1 ETXEN (1) PB2 ETX0 (1) PB3 ETX1 (1) PB4 ECRSDV/ERXDV (1) PB5 ERX0 (1) PB6 ERX1 (1) PB7 ...

  • Page 53

    PIO Controller C Multiplexing Table 11-4. Multiplexing on PIO Controller C (PIOC) I/O Line Peripheral A PC0 PC1 PC2 D0 PC3 D1 PC4 D2 PC5 D3 PC6 D4 PC7 D5 PC8 D6 PC9 D7 PC10 D8 PC11 D9 PC12 ...

  • Page 54

    PIO Controller D Multiplexing Table 11-5. Multiplexing on PIO Controller D (PIOD) I/O Line Peripheral A PD0 A10 PD1 A11 PD2 A12 PD3 A13 PD4 A14 PD5 A15 PD6 A16/BA0 PD7 A17/BA1 PD8 A21/NANDALE PD9 A22/NANDCLE PD10 NWR1/NBS1 PD11 ...

  • Page 55

    PIO Controller E Multiplexing Table 11-6. Multiplexing on PIO Controller E (PIOE) I/O Line Peripheral A PE0 A19 PE1 A20 PE2 A21/NANDALE PE3 A22/NANDCLE PE4 A23 PE5 NCS4 PE6 NCS5 PE7 PE8 PE9 TIOA3 PE10 TIOB3 PE11 TIOA4 PE12 ...

  • Page 56

    PIO Controller F Multiplexing Table 11-7. Multiplexing on PIO Controller F (PIOF) I/O Line Peripheral A PF0 SPI1_NPCS1 PF1 SPI1_NPCS2 PF2 SPI1_NPCS3 PF3 PWMH3 PF4 CTS3 PF5 RTS3 SAM3X/A SAM3X Peripheral B Extra Function Comments 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 ...

  • Page 57

    Embedded Peripherals Overview 12.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with – Serial memories, such as DataFlash and 3-wire EEPROMs – ...

  • Page 58

    Support for two PDC channels with connection to receiver and transmitter – Connection to Peripheral DMA Controller or DMA Controller (TWI0) Channel 12.4 USART • Programmable Baud Rate Generator • 9-bit full-duplex synchronous or asynchronous serial communications ...

  • Page 59

    Generation of the Wakeup signal • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Interfaced with Peripheral DMA (PDC) Channels to Reduce Processor Overhead (All USARTs) and with the DMA Controller (DMAC) (USART0 and 1) 12.5 Serial ...

  • Page 60

    Pulse Width Modulation Controller (PWM) • One Eight-channel (SAM3A and 144-pin SAM3X) or One Four-channel (100-pin SAM3X) 16- bit PWM Controller, 16-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing ...

  • Page 61

    Each Slot for either a High Speed MultiMediaCard Bus ( Cards • Support for Stream, Block and Multi-block Data Read and Write • Supports Connection to DMA Controller (DMAC) – Minimizes Processor Intervention for ...

  • Page 62

    Automatic Window Comparison of Converted Values • Write Protect Registers 12.11 Digital-to-Analog Converter (DAC) • 2 channels, 12-bit DAC • mega-sample conversion rate in single channel mode • Flexible conversion range • Multiple trigger sources for ...

  • Page 63

    FIFO and 128-byte receive FIFO • Automatic pad and CRC generation on transmitted frames • Automatic discard of frames received with errors • Address checking logic supports up to four specific 48-bit addresses • Support Promiscuous Mode ...

  • Page 64

    Package Drawings The SAM3X/A series devices are available in QFP (LQFP or PQFP) and LFBGA packages. Figure 13-1. 100-lead LQFP Package Drawing Note : 1. This drawing is for general information only. Refer to JEDEC Drawing MS-026 for additional ...

  • Page 65

    Figure 13-2. 100-ball LFBGA Package Drawing 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 SAM3X/A SAM3X ...

  • Page 66

    Figure 13-3. 144-lead LQFP Package Drawing SAM3X/A SAM3X 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 ...

  • Page 67

    Figure 13-4. 144-ball LFBGA Package Drawing All dimensions are in mm 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 SAM3X/A SAM3X ...

  • Page 68

    Marking All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: where • “YY”: manufactory year • “WW”: manufactory week • “V”: revision “XXXXXXXXX”: lot number SAM3X/A ...

  • Page 69

    ... Ordering Information Table 14-1. SAM3X/A Ordering Information Ordering Code MRL ATSAM3A4CA-AU A ATSAM3A8CA-AU A ATSAM3A4CA-CU A ATSAM3A8CA-CU A ATSAM3X4CA-AU A ATSAM3X8CA-AU A ATSAM3X4CA-CU A ATSAM3X8CA-CU A ATSAM3X4EA-AU A ATSAM3X8EA-AU A ATSAM3X4EA-CU A ATSAM3X8EA-CU A 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 Flash (Kbytes) Package 256 LQFP100 512 LQFP100 256 LFBGA100 512 LFBGA100 256 ...

  • Page 70

    Revision History Doc. Rev Comments 11057AS First issue SAM3X/A SAM3X Change Request Ref. 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 ...

  • Page 71

    SAM3X/A SAM3X 11057AS–ATARM–10-Feb-12 11057AS–ATARM–10-Feb-12 ...

  • Page 72

    ... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2011 Atmel Corporation. All rights reserved. Atmel trademarks of Atmel Corporation or its subsidiaries. ARM trademarks of ARM Ltd. Other terms and product names may be trademarks of others. International ...