AD9286 Analog Devices, AD9286 Datasheet
AD9286
Specifications of AD9286
Related parts for AD9286
AD9286 Summary of contents
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... Each ADC operates 250 MSPS conversion rate with outstanding dynamic performance. The AD9286 takes a single sample clock and, with an on-chip clock divider, time interleaves the two ADC cores (each running at one-half the clock frequency) to achieve the rated 500 MSPS. ...
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... AD9286 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 DC Specifications ......................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 SPI Timing Specifications ........................................................... 6 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ...
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... Full 0 Full 0 Full Full Full Full Full Full Full Full 0.97 Full Full 1.7 Full 1.7 Full Full Full Full Rev Page AD9286 Typ Max Unit Bits ±0.2 ±0.4 LSB ±0.1 ±0.3 LSB Guaranteed ±0.4 ±2 ±2 ±2 ±0.4 ±2 ±0.05 ±0 ±2 ppm/° ...
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... AD9286 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, VIN = −1.0 dBFS differential input, optimum timing value set, unless otherwise noted. Table 2. Parameter SIGNAL-TO-NOISE RATIO (SNR 10.3 MHz MHz 96.6 MHz 220 MHz IN SIGNAL-TO-NOISE-AND-DISTORTION (SINAD 10.3 MHz MHz 96.6 MHz ...
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... Full 1.2 Full 0 Full 50 57 Full 5 0.4 − − 25°C 30 25°C 2 Full 290 345 Full 1.15 1.25 Offset binary Rev Page AD9286 Max Unit p-p AVDD + 1.6 V 3.6 V 0.8 V +10 μA +10 μA kΩ pF DRVDD + 0 μA 50 μA − kΩ pF DRVDD + 0 ...
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... AD9286 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate CLK Period (t ) CLK CLK Pulse Width High ( DATA OUTPUT PARAMETERS Data Propagation Delay ( DCO Propagation Delay (t ...
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... M – SKEW N – – – – – 9 Rev Page AD9286 – – – – – – 7 ...
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... AD9286 M – 1 VIN1+, VIN1– N – 2 VIN2+, VIN2– CLK+ CLK– AUXCLK– AUXCLK+ DCO+, DCO– DATA Figure 5. Output Timing Diagram, Sample Mode = Simultaneous, AUXCLKEN = 1, CLK and AUXCLK Out of Phase – ...
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... V to AVDD + 0.2 V Package Type −0 AVDD + 0.2 V −0 DRVDD + 0.3 V 48-Lead LFCSP (CP-48-12) −0 DRVDD + 0.3 V −0 DRVDD + 0.3 V ESD CAUTION −65°C to +125°C −40°C to +85°C 300°C 150°C Rev Page AD9286 θ θ Unit JA JC 30.4 2.9 °C/W ...
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... D7− (MSB) 24 D6+ 23 D6− AVDD 1 PIN 1 AVDD 2 INDICATOR 3 4 RBIAS 5 AD9286 6 TOP VIEW DRGND 7 (Not to Scale) DRVDD D1– 11 D1+ 12 THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB ANALOG GROUND TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. ...
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... Output Data 0—True. Output Output Data 0—Complement. Output Data Clock Output—True. Output Data Clock Output—Complement. Input SPI Serial Clock. Input/output SPI Serial Data I/O (SDIO)/Power-Down Input in External Mode (PWDN). Input SPI Chip Select (Active Low). Rev Page AD9286 ...
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... AD9286 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 500 MSPS, DCS enable, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample 25°C, unless otherwise noted 500MSPS 4.3MHz @ –1dBFS SNR = 48.4dB (49.4dBFS) –20 ENOB = 7.7 SFDR = 70.0dBc –40 SECOND HARMONIC –60 THIRD HARMONIC – ...
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... Rev Page 100 95 +85° +25° –40° –3 –2 – COARSE TIMING ADJUSTMENT (Bits 128 160 192 OUTPUT CODE Figure 17. INL Error with f = 4.3 MHz IN AD9286 2 3 224 256 ...
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... AD9286 EQUIVALENT CIRCUITS AVDD AVDD 1.2V 10kΩ 10kΩ CLK+ Figure 18. Clock Inputs AVDD AVDD BUF VIN+ 8kΩ BUF AVDD 8kΩ BUF VIN– Figure 19. Analog Inputs (V CML DRVDD DRVDD 30kΩ 350Ω CSB Figure 20. CSB AVDD CLK– V CML ~1 ...
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... See the Memory Map Register Descriptions section for more details. RBIAS The AD9286 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor, which is used to set the master current reference of the ADC core, should have a 1% tolerance ...
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... CLK− and AUXCLK+ and AUXCLK −, when necessary. Figure 26 and Figure 27 show two preferred methods for clocking the AD9286. A low jitter clock source is converted from a single- ended signal to a differential signal using either an RF transformer balun. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9286 to approximately 0 ...
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... ADC core. If the user desires to operate the AD9286 as a dual 8-bit, 250 MSPS converter and supply only a single clock, this is achieved by setting sample mode to simultaneous, with the AUXCLKEN pin tied to AGND ...
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... DIGITAL OUTPUTS Digital Output Enable Function ( OE ) The AD9286 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the is set to logic level high, the output drivers for both data buses are placed into a high impedance state. ...
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... AD9286. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9286 signal path. Perform the BIST test after a reset to ensure that the part known state. During BIST, data from an internal pseudorandom noise (PN) source is driven through the digital datapath of both channels, starting at the ADC block output ...
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... AD9286 SERIAL PORT INTERFACE (SPI) The AD9286 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...
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... The pins described in Table 10 constitute the physical interface between the programming device of the user and the serial port of the AD9286. The SCLK and CSB pins function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback ...
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... If the entire address location is open omitted from the SPI map (for example, Address 0x13) and should not be written. Default Values After the AD9286 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 13). ...
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... PN23 sequence 110: PN9 sequence 111: one-/zero-word toggle BIST init Open BIST enable 0x00 AD9286 Default Notes/ Comments Nibbles are mirrored so that LSB- first or MSB- first mode registers correctly, ...
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... AD9286 Addr Register Bit 7 (Hex) Name (MSB) Bit 6 0x0F ADC input (global/local) 0x10 Offset (local) 0x14 Output Open mode (local) 0x16 Output DCO invert phase (global) 0x18 Voltage Open reference (global) 0x24 MISR LSB (local) 0x25 MISR MSB (local) 0x37 Timing ...
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... External Rev Page AD9286 Full Scale (V) 1.013 1.028 1.044 1.060 1.075 1.091 1.106 1.122 1.138 1.153 1.169 1.184 1.200 1.216 1.231 1.247 1.262 1 ...
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... VCM The VCM pin should be decoupled to ground with a 0.1 μF capacitor. RBIAS The AD9286 requires that a 10 kΩ resistor be placed between the RBIAS pin and ground. This resistor, which sets the master current reference of the ADC core, should have at least a 1% tolerance. ...
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... Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 4.70 EXPOSED 4.60 SQ PAD 4.50 (BOTTOM VIEW 0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. AD9286 Package Option CP-48-12 CP-48-12 ...
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... AD9286 NOTES ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09338-0-3/11(A) Rev Page ...