AD7606 Analog Devices, AD7606 Datasheet - Page 7

• Manufacturer Part Number: AD7606
• Description: 8-Channel DAS with 16-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7606

• Resolution (bits): 16bit
• # Chan: 8
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

Data Sheet
TIMING SPECIFICATIONS
AV
Table 3.
Parameter
PARALLEL/SERIAL/BYTE MODE
PARALLEL/BYTE READ
t
t
OPERATION
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CC
CYCLE
CONV
WAKE-UP STANDBY
WAKE-UP SHUTDOWN
RESET
OS_SETUP
OS_HOLD
1
2
3
4
5
6
7
8
9
10
11
12
3
Internal Reference
External Reference
= 4.75 V to 5.25 V, V
2
DRIVE
= 2.3 V to 5.25 V, V
Min
3.45
7.87
16.05
33
66
133
257
50
20
20
25
25
0
25
0
0
16
21
25
32
15
22
Logic Input Levels)
Limit at T
(0.1 × V
0.9 × V
Typ
4
3
2
DRIVE
MIN
DRIVE
, T
and
REF
MAX
Max
5
9.7
4.15
9.1
18.8
39
78
158
315
100
30
13
40
0.5
25
= 2.5 V external reference/internal reference, T
Min
3.45
7.87
16.05
33
66
133
257
50
20
20
25
25
0
25
0
0
19
24
30
37
15
22
Logic Input Levels)
Limit at T
(0.3 × V
Rev. C | Page 7 of 36
0.7 × V
Typ
4
3
2
DRIVE
MIN
DRIVE
, T
and
MAX
Max
5
9.4
10.7
4.15
9.1
18.8
39
78
158
315
100
30
13
45
0.5
25
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
1/throughput rate
Parallel mode, reading during or after conversion; or
serial mode: V
conversion using D
Serial mode reading after a conversion; V
Serial mode reading after a conversion; V
D
Conversion time
Oversampling off; AD7606
Oversampling off; AD7606-6
Oversampling off; AD7606-4
Oversampling by 2; AD7606
Oversampling by 4; AD7606
Oversampling by 8; AD7606
Oversampling by 16; AD7606
Oversampling by 32; AD7606
Oversampling by 64; AD7606
STBY rising edge to CONVST x rising edge; power-up
time from standby mode
STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
STBY rising edge to CONVST x rising edge; power-up
time from shutdown mode
RESET high pulse width
BUSY to OS x pin setup time
BUSY to OS x pin hold time
CONVST x high to BUSY high
Minimum CONVST x low pulse
Minimum CONVST x high pulse
BUSY falling edge to CS falling edge setup time
Maximum delay allowed between CONVST A, CONVST
B rising edges
Maximum time between last CS rising edge and BUSY
falling edge
Minimum delay between RESET low to CONVST x high
CS to RD setup time
CS to RD hold time
RD low pulse width
V
V
V
V
RD high pulse width
CS high pulse width (see Figure 5); CS and RD linked
DRIVE
DRIVE
DRIVE
DRIVE
OUT
AD7606/AD7606-6/AD7606-4
A and D
above 4.75 V
above 3.3 V
above 2.7 V
above 2.3 V
A
= T
OUT
MIN
DRIVE
B lines
to T
= 3.3 V to 5.25 V, reading during a
OUT
MAX
A and D
, unless otherwise noted.
OUT
B lines
DRIVE
DRIVE
= 2.3 V,
= 2.7 V
1