AD7606-4 Analog Devices, AD7606-4 Datasheet - Page 28

• Manufacturer Part Number: AD7606-4
• Description: 4-Channel DAS with 16-Bit, Bipolar, Simultaneous Sampling ADC
• Manufacturer: Analog Devices

Specifications of AD7606-4

• Resolution (bits): 16bit
• # Chan: 4
• Sample Rate: 200kSPS
• Interface: Par,Ser,SPI
• Analog Input Type: SE-Bip
• Ain Range: Bip 10V,Bip 5.0V
• Adc Architecture: SAR
• Pkg Type: QFP

AD7606/AD7606-6/AD7606-4
The CS falling edge takes the data output lines, D
out of three-state and clocks out the MSB of the conversion
result. The rising edge of SCLK clocks all subsequent data bits
onto the serial data outputs, D
can be held low for the entire serial read operation, or it can be
pulsed to frame each channel read of 16 SCLK cycles. Figure 46
shows a read of eight simultaneous conversion results using two
D
to access data from the AD7606, and CS is held low to frame the
entire 64 SCLK cycles. Data can also be clocked out using just
one D
used to access all conversion data because the channel data is
output in ascending order. For the AD7606 to access all eight
conversion results on one D
is required. These 128 SCLK cycles can be framed by one CS
signal, or each group of 16 SCLK cycles can be individually
framed by the CS signal. The disadvantage of using just one
D
after conversion. The unused D
in serial mode. For the AD7606, if D
D
V5, V6, V7, V8, V1, V2, V3, and V4; however, the FRSTDATA
indicator returns low after V5 is read on D
and the AD7606-4, if D
the channel results are output in the following order: V4, V5, V6,
V1, V2, and V3 for the AD7606-6; and V3, V4, V1, and V2 for
the AD7606-4.
Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the AD7606/AD7606-6/
AD7606-4 in serial mode. The SCLK input signal provides the
clock source for the serial read operation. The CS goes low to
access the data from the AD7606/AD7606-6/AD7606-4.
OUT
OUT
OUT
lines on the AD7606. In this case, a 64 SCLK transfer is used
line is that the throughput rate is reduced if reading occurs
line, the channel results are output in the following order:
OUT
line, in which case it is recommended that D
OUT
B is to be used as a single D
OUT
D
D
SCLK
OUT
OUT
OUT
OUT
CS
line, a total of 128 SCLK cycles
A
B
A and D
line should be left unconnected
OUT
B is to be used as a single
OUT
OUT
B. For the AD7606-6
B. The CS input
Figure 46. AD7606 Serial Interface with Two D
OUT
A and D
V1
V5
OUT
OUT
A be
line,
OUT
Rev. C | Page 28 of 36
B,
V2
V6
The falling edge of CS takes the bus out of three-state and clocks
out the MSB of the 16-bit conversion result. This MSB is valid
on the first falling edge of the SCLK after the CS falling edge.
The subsequent 15 data bits are clocked out of the AD7606/
AD7606-6/AD7606-4 on the SCLK rising edge. Data is valid on
the SCLK falling edge. To access each conversion result, 16 clock
cycles must be provided to the AD7606/AD7606-6/AD7606-4.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of
CS takes FRSTDATA out of three-state and sets the FRSTDATA
pin high, indicating that the result from V1 is available on the
D
a logic low following the 16
are read on D
V1 is being output on this serial data output pin. It goes high
only when V1 is available on D
available on D
READING DURING CONVERSION
Data can be read from the AD7606/AD7606-6/AD7606-4 while
BUSY is high and the conversions are in progress. This has little
effect on the performance of the converter, and it allows a faster
throughput rate to be achieved. A parallel, parallel byte, or serial
read can be performed during conversions and when oversampling
may or may not be in use. Figure 3 shows the timing diagram for
reading while BUSY is high in parallel or serial mode. Reading
during conversions allows the full throughput rate to be achieved
when using the serial interface with V
Data can be read from the AD7606 at any time other than on
the falling edge of BUSY because this is when the output data
registers are updated with the new conversion data. Time t
outlined in Table 3, should be observed in this condition.
V3
V7
OUT
A output data line. The FRSTDATA output returns to
OUT
OUT
Lines
OUT
V4
V8
B, the FRSTDATA output does not go high when
B for the AD7606).
64
th
SCLK falling edge. If all channels
OUT
A (and this is when V5 is
DRIVE
above 4.75 V.
Data Sheet
6
, as