AD7195 Analog Devices, AD7195 Datasheet
AD7195
Specifications of AD7195
Available stocks
Related parts for AD7195
AD7195 Summary of contents
Page 1
... Data acquisition Medical and scientific instrumentation GENERAL DESCRIPTION The AD7195 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC ...
Page 2
... AD7195 TABLE OF CONTENTS Features .............................................................................................. 1 Interface ............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Typical Performance Characteristics ........................................... 11 RMS Noise and Resolution ............................................................ 13 4 Sinc Chop Disabled ................................................................... 13 3 Sinc Chop Disabled ...
Page 3
... Rev Page AD7195 , REFIN(−) = AGND, MCLK = 4.92 MHz Test Conditions/Comments Chop disabled 4 Chop enabled, sinc filter 3 Chop enabled, sinc filter > 1, sinc filter > 4, sinc filter ...
Page 4
... AD7195 Parameter Min External Clock @ 50 Hz 100 ANALOG INPUTS Differential Input Voltage Ranges −(AV − DD 1.25 V)/gain 2 Absolute AIN Voltage Limits Unbuffered Mode AGND − 0.05 Buffered Mode AGND + 0.25 Analog Input Current Buffered Mode 2 Input Current −2 −4.5 ...
Page 5
... Rev Page AD7195 1 Test Conditions/Comments 100 μA DD SOURCE 100 μA DD SINK 200 μA DD SOURCE 1 SINK gain = 1, buffer off gain = 1, buffer on gain = 8, buffer off gain = 8, buffer on ...
Page 6
... AD7195 TIMING CHARACTERISTICS 5.25 V, AGND = DGND = 0 V, Input Logic Input Logic otherwise noted. Table 2. Parameter Limit at T READ AND WRITE OPERATIONS t 100 3 t 100 4 READ OPERATION ...
Page 7
... Figure 2. Load Circuit for Timing Characterization CS ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) MSB LSB I = INPUT OUTPUT Figure 4. Write Cycle Timing Diagram Rev Page 5V 3V LSB AD7195 ...
Page 8
... AD7195 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 3. Parameter Rating AV to AGND −0 +6 AGND −0 +6 AGND to DGND −0 +0.3 V Analog Input Voltage to AGND −0 Reference Input Voltage to AGND −0 Digital Input Voltage to DGND − ...
Page 9
... Scale AGND REFIN(–) REFIN(+) AINCOM 8 17 NOTES CONNECT. 2. CONNECT EXPOSED PAD TO AGND. Figure 5.Pin Configuration is independent and AGND + 1 V. The nominal reference voltage, (REFIN(+) − REFIN(−)), Rev Page AD7195 . − ...
Page 10
... Master Clock Signal for the Device. The AD7195 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7195 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected ...
Page 11
... Figure 9. Noise Distribution Histogram ( REF 0 100 200 300 400 500 600 700 800 SAMPLES = 5 V, Output Data Rate = 4800 Hz, Gain = 1, REF 4 Chop Disabled, Sinc Filter) 8,388,660 8,388,700 8,388,740 8,388,780 CODE Figure 11. Noise Distribution Histogram ( REF AD7195 8,388,920 4 Filter) 900 1000 8,388,820 4 Filter) ...
Page 12
... AD7195 3.0 2.0 1.0 0 –1.0 –2.0 –3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0 0.5 V (V) IN Figure 12. INL (Gain = –2 –4 –6 –0.020 –0.015 –0.010 –0.005 0 0.005 V (V) IN Figure 13. INL (Gain = 128 –60 –40 – TEMPERATURE (° ...
Page 13
... The tables in this section show the rms noise, peak-to-peak noise, effective resolution, and noise-free (peak-to-peak) resolu- tion of the AD7195 for various output data rates and gain settings, with chop disabled and chop enabled for the sinc filters. The numbers given are for the bipolar input range with the external 5 V reference ...
Page 14
... AD7195 3 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 4.7 639.4 640 7.5 400 480 10 300 150 20 16 300 10 5 960 3.13 2 2400 1.25 1 4800 0.625 Table 10. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate ...
Page 15
... Gain of 32 Gain of 64 Gain of 128 24 (21.7) 24 (21.7) 23.6 (20.9) 23.9 (21.4) 23.9 (21.4) 23.3 (20.7) 23.8 (21.3) 23.8 (21.1) 23.2 (20.6) 23.2 (20.6) 22.7 (20.2) 21.9 (19.3) 23 (20.5) 22.6 (19.9) 21.8 (19.1) 22.5 (20) 22 (19.3) 21.1 (18.4) 22.1 (19.5) 21.5 (18.9) 20.6 (18) 21.3 (18.6) 20.7 (18.1) 19.8 (17.2) 20.6 (18) 20 (17.3) 19.1 (16.5) 19.6 (16.9) 19.3 (16.5) 18.5 (15.8) AD7195 134 200 Gain of 128 120 134 219 304 502 850 1345 1 ...
Page 16
... AD7195 3 SINC CHOP ENABLED Table 15. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.56 1282 640 2.5 800 480 3.33 600 96 16.6 120 80 20 100 100 20 5 320 6.25 2 800 2.5 1 1600 1.25 Table 16. Peak-to-Peak Noise (nV) vs. Gain and Output Data Rate ...
Page 17
... OF14 OF13 OF12 OF7 OF6 OF5 OF4 FS23 (MSB) FS22 FS21 FS20 FS15 FS14 FS13 FS12 FS7 FS6 FS5 FS4 Rev Page AD7195 Bit 3 Bit 2 Bit 1 Bit 0 CREAD CHD2 CHD1 CHD0 CLK1 CLK0 0 0 SINGLE REJ60 FS9 FS8 FS3 ...
Page 18
... AD7195 COMMUNICATIONS REGISTER (RS2, RS1, RS0 = The communications register is an 8-bit write-only register. All communications to the part must start with a write operation to the communications register. The data written to the communications register determines whether the next operation is a read or a write operation and in which register this operation takes place ...
Page 19
... SR4 SR3 SR2 PARITY(0) 0 CHD2(0) MR20 MR19 MR18 DAT_STA(0) CLK1(1) CLK0(0) MR12 MR11 MR10 0 SINGLE(0) REJ60(0) MR4 MR3 MR2 FS4(0) FS3(0) FS2(0) Rev Page AD7195 SR1 SR0 CHD1(0) CHD0(0) MR17 MR16 0 0 MR9 MR8 FS9(0) FS8(0) MR1 MR0 FS1(0) FS0(0) ...
Page 20
... This bit must be programmed with a Logic 0 for correct operation. MR11 SINGLE Single cycle conversion enable bit. When this bit is set, the AD7195 settles in one conversion cycle so that it functions as a zero-latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. ...
Page 21
... Power-down mode. In power-down mode, all AD7195 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7195 for settling reasons. The external crystal, if selected, remains active. ...
Page 22
... CON22 ACX AC excitation enable bit. If the signal source to the AD7195 is ac excited, this bit must be set to 1. For dc-excited inputs, this bit must be 0. With the ACX bit at 1, the AD7195 assumes that the voltage at the AIN(+)/AIN(–) and REFIN(+)/REFIN(–) input terminals are reversed on alternate input sampling cycles (that is, chopped) ...
Page 23
... CHD0) identify the channel from which the conversion originated. ID REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0xA6) The identification number for the AD7195 is stored in the ID register. This is a read-only register. GPOCON REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written ...
Page 24
... The power-on reset value is automatically overwritten if an internal or system zero-scale calibration is initiated by the user. The AD7195 must be placed in power- down mode or idle mode when writing to the offset register. FULL-SCALE REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x5XXXX0) The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC ...
Page 25
... The AD7195 has a 4-wire SPI. The on-chip registers are accessed via the serial interface. Clock The AD7195 has an internal 4.92 MHz clock. Either this clock or an external clock can be used as the clock source to the AD7195. The internal clock can also be made available on a pin if a clock source is required for external circuitry ...
Page 26
... If the voltage between the REFIN(+) and REFIN(−) pins is between 0.3 V and 0.6 V, the AD7195 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set the AD7195 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. ...
Page 27
... AIN1 pin is 2 3.75 V when a 2.5 V reference is used. If AINCOM is 2.5 V and the AD7195 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input range on AIN1 is 1. 3.75 V. ...
Page 28
... The serial interface of the AD7195 consists of four signals DIN, SCLK, and DOUT/ RDY . The DIN line is used to transfer data into the on-chip registers and DOUT/ RDY is used for accessing data from the on-chip registers ...
Page 29
... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7195 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
Page 30
... AD7195 Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7195 converts continuously, and the RDY bit in the status register goes low each time a conversion is complete low, the DOUT/ RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the communications register, indicating that the next operation is a read of the data register ...
Page 31
... Continuous Read Rather than write to the communications register each time a conversion is complete to access the data, the AD7195 can be configured so that the conversions are placed on the DOUT/ RDY line automatically. By writing 01011100 to the communications register, the user need only apply the appropriate number of SCLK cycles to the ADC, and the conversion word is automatically placed on the DOUT/ RDY line when a conversion is complete ...
Page 32
... In a system using multiple AD7195 devices, a common signal to their SYNC pins synchronizes their operation. This is normally done after each AD7195 has performed its own calibration or has calibration coefficients loaded into its calibration registers ...
Page 33
... The gain error of the AD7195 is factory calibrated at a gain of 1 with power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically Table 28 shows the typical uncalibrated gain error for the different gain settings ...
Page 34
... AD7195 DIGITAL FILTER The AD7195 offers a lot of flexibility in the digital filter. The device has four filter options. The device can be operated 3 4 with a sinc or sinc filter, chop can be enabled or disabled, and zero latency can be enabled. The option selected affects the output data rate, settling time, and 50 Hz/60 Hz rejection. The following sections describe each filter type, indicating the available output data rates for each filter option ...
Page 35
... FREQUENCY (Hz) 4 Figure 29. Sinc Filter Response (FS[9:0] = 80) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –110 FREQUENCY (Hz) 4 Figure 30. Sinc Filter Response (FS[9:0] = 480) AD7195 4 filter provides 120 150 4 120 150 ...
Page 36
... AD7195 The output data rate when zero latency is disabled and 12.5 Hz when zero latency is enabled. Figure 31 shows the 4 frequency response of the sinc filter. The filter provides 50 Hz ±1 Hz and 60 Hz ± rejection minimum, assuming a stable 4.92 MHz master clock. 0 –10 – ...
Page 37
... Rev Page 100 FREQUENCY (Hz) 3 Figure 36. Sinc Filter Response (FS[9: 120 FREQUENCY (Hz) 3 Figure 37. Sinc Filter Response (FS[9:0] = 80) AD7195 3 filter when 3 filter gives 125 150 3 filter has 150 ...
Page 38
... AD7195 Simultaneous 50 Hz and 60 Hz rejection is obtained when FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in Figure 38. The output data rate when zero latency is disabled and 3.3 Hz when zero latency is enabled. The sinc filter has rejection of 100 dB minimum ± and 60 Hz ± 1 Hz. ...
Page 39
... Rev Page 100 FREQUENCY (Hz) 4 Figure 43. Sinc Filter Response (FS[9:0] = 96, Chop Enabled) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 100 FREQUENCY (Hz) 4 Filter Response (FS[9:0] = 96, Chop Enabled, REJ60 = 1) AD7195 125 150 125 150 ...
Page 40
... AD7195 3 CHOP ENABLED (SINC FILTER) With chop enabled, the ADC offset and offset drift are minimized. The analog input pins are continuously swapped. With the analog input pins connected in one direction, the settling time of the sinc filter is allowed and a conversion is recorded. The analog input pins invert and another settled conversion is obtained ...
Page 41
... For output dates rates greater than 1 kHz, the sinc SUMMARY OF FILTER OPTIONS The AD7195 has several filter options. The filter that is chosen affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. Table 35 shows some sample configurations and the corres- ponding performance in terms of throughput, settling time and 50 Hz/60 Hz rejection ...
Page 42
... AD7195 to prevent noise coupling. The power supply lines to the AD7195 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals ...
Page 43
... WEIGH SCALES Figure 50 shows the AD7195 being used in a weigh scale applica- tion which uses ac excitation. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– ...
Page 44
... ORDERING GUIDE 1 Model Temperature Range AD7195BCPZ –40°C to +105°C AD7195BCPZ-RL –40°C to +105°C AD7195BCPZ-RL7 –40°C to +105° RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 5.10 0.30 5 ...