AD7625 Analog Devices, AD7625 Datasheet
AD7625
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AD7625 Summary of contents
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... All converted results are available on a single LVDS self-clocked or echoed-clock serial interface, reducing external hardware connections. The AD7625 is housed in a 32-lead × LFCSP with operation specified from −40°C to +85°C. Resolution (Bits) 1 MSPS to <2 MSPS ...
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... Theory of Operation ...................................................................... 13 Circuit Information .................................................................... 13 Converter Information .............................................................. 13 Transfer Functions ..................................................................... 14 Analog Inputs ............................................................................. 14 Typical Connection Diagram ................................................... 15 Driving the AD7625 ................................................................... 16 Voltage Reference Options ........................................................ 17 Power Supply ............................................................................... 18 Digital Interface .......................................................................... 19 Applications Information .............................................................. 21 Layout, Decoupling, and Grounding ....................................... 21 ...
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... REF AD7625 Unit Bits μA ns MSPS LSB Bits LSB LSB LSB ppm/°C LSB ppm/°C LSB LSB MHz ps rms V ppm/° ...
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... Using an external reference. 2 The ANSI-644 LVDS specification has a minimum output common mode (V 3 Power dissipation is for the AD7625 device only. In self-clocked interface mode dissipated in the 100 Ω terminator. In echoed-clock interface mode dissipated in two 100 Ω terminators. Test Conditions/Comments Min R = 100 Ω ...
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... CLK f CLK t 0 DCO CLKD − Divide this time by the number of bits (n) that are read. In echoed-clock interface CYC MSB CLK Rev Page AD7625 , unless otherwise noted. MAX Typ Max Unit 10,000 145 ns 110 ns 4 3.33 ns 250 ...
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... AD7625 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Analog Inputs/Outputs IN+, IN− to GND 1 2 REF to GND VCM, CAP2 to GND CAP1, REFIN to GND Supply Voltage VDD1 VDD2, VIO Digital Inputs to GND Digital Outputs to GND Input Current to Any Pin Except 3 Supplies Operating Temperature Range (Commercial) ...
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... IN– CAP1 3 22 VCM REFIN 4 AD7625 21 VDD1 EN0 5 20 TOP VIEW 6 19 VDD1 EN1 (Not to Scale VDD2 VDD2 8 17 CLK+ CNV– NOTES 1. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS. Figure 2. Rev Page AD7625 ...
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... AD7625 1 Pin No. Mnemonic Type Description 25, 26, 28 CAP2 AO Connect all three CAP2 pins together and decouple them with the shortest trace possible to a single 10 μF, low ESR, low ESL capacitor. The other side of the capacitor must be placed close to Pin 27 (GND). 27 GND P Ground. Return path for the 10 μF capacitor connected to Pin 25, Pin 26, and Pin 28. ...
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... FREQUENCY (kHz) 0 INPUT TONE = 100kHz SNR = 92.91dB –20 SINAD = 92.55dB THD = –103.11dB SFDR = –103.41dB –40 –60 –80 0 0.5 1.0 1.5 2.0 FREQUENCY (MHz) Figure 7. FFT 100 kHz Input Tone 1.0 0.8 0.6 0.4 0 16,384 32,768 49,152 CODE Figure 8. Integral Nonlinearity vs. Code AD7625 2.5 3.0 65,536 ...
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... AD7625 –94 –96 –0.5dBFS –98 –100 –1dBFS –102 –104 –106 –108 –110 –5dBFS –112 –114 –116 INPUT FREQUENCY (kHz) Figure 9. THD at Input Amplitudes of −0.5 dBFS to −10 dBFS vs. Frequency 93.8 93.6 DYNR vs. TEMP INTERNAL REF DYNR vs. TEMP EXTERNAL REF 93.4 93.2 93.0 92.8 SNR vs. TEMP EXTERNAL REF 92 ...
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... FECC FECD Figure 17. Histogram of 262,144 Conversions Input 33 0 FECD FECE Rev Page 129,601 262,144 SAMPLES 128,084 STD DEVIATION = 0.5329 2329 2130 0 FEC6 FEC7 FEC8 FEC9 FECA CODE (HEX) at the Code Transition (Internal Reference) AD7625 0 FECB ...
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... AD7625 TERMINOLOGY Common-Mode Rejection Ratio (CMRR) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency the power p-p sine wave applied to the common-mode voltage of V frequency CMRR (dB) = 10log(Pf/ where the power at frequency f in the ADC output. ...
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... MSPS). The device typically consumes 135 mW. The AD7625 offers the added functionality of a high performance on-chip reference and on-chip reference buffer. The AD7625 is specified for use with 5 V and 2.5 V supplies (VDD1, VDD2). The interface from the digital host to the AD7625 uses 2.5 V logic only. The AD7625 uses an LVDS interface to transfer data conversions. The CNV+ and CNV− ...
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... V 0x1000 ANALOG INPUTS The analog inputs, IN+ and IN−, applied to the AD7625 must be 180° out of phase with each other. Figure 20 shows an equivalent circuit of the input structure of the AD7625. The two diodes provide ESD protection for the analog inputs, IN+ and IN− ...
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... TO ENABLE SELF-CLOCKED MODE, TIE DCO+ TO GND USING A PULL-DOWN RESISTOR. 6 CONNECT PIN 19 AND PIN 20 TO VDD1 SUPPLY; ISOLATE FROM PIN 1 USING A FERRITE BEAD SIMILAR TO WURTH 74279266. 7 SEE THE DRIVING THE AD7625 SECTION FOR DETAILS ON AMPLIFIER CONFIGURATIONS. 8 SEE THE VOLTAGE REFERENCE OPTIONS SECTION FOR DETAILS. 8 ...
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... V to 4.096 V, produces a differential ±4.096 V with midscale at 2.048 V. The one-pole filter using Ω and provides a corner frequency of 86 MHz. The VCM output of the AD7625 can be buffered and then used to provide the required 2.048 V common-mode voltage ...
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... VOLTAGE REFERENCE OPTIONS The AD7625 allows flexible options for creating and buffering the reference voltage. The AD7625 conversions refer to 4.096 V only. The various options creating this 4.096 V reference are controlled by the EN1 and EN0 pins (see Table 8). ADR434 V+ ADR444 SETTING EN1 = 1 AND EN0 = 0 DISABLES THE INTERNAL REFERENCE AND REFERENCE BUFFER ...
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... VIO and VDD2 pins using separate traces and also to decouple each pin separately. The 5 V and 2.5 V supplies required for the AD7625 can be generated using Analog Devices, Inc., low dropout regulators (LDOs) such as the ADP3330-2.5, ADP3330-5, ADP3334, and ADP1708 ...
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... CYC The two methods for acquiring the digital data output of the AD7625 via the LVDS interface are described in the following sections. Echoed-Clock Interface Mode The digital operation of the AD7625 in echoed-clock interface mode is shown in Figure 29. This interface mode, requiring only a shift register on the digital host, can be used with many digital hosts (FPGA, shift register, microprocessor, and so on) ...
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... Figure 30. This interface mode reduces the number of wires between ADCs and the digital host to two LVDS pairs per AD7625 (CLK± and D± single pair if sharing a common CLK± using multiple AD7625 devices. Self-clocked interface mode facilitates the design of boards that use multiple AD7625 devices ...
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... Pin 28 by widening the PCB traces connecting these pins. A similar approach should be taken in the connections used for the reference pins of the AD7625. Connect Pin 29, Pin 30, and Pin 32 together using widened PCB traces to reduce inductance. In internal or external reference mode, a 4.096 V reference voltage is output on Pin 29, Pin 30, and Pin 32. Decouple these pins to Pin 31 using a 10 μ ...
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... Temperature Range 1 AD7625BCPZ −40°C to +85°C 1 AD7625BCPZ-RL7 −40°C to +85° EVAL-AD7625EDZ EVAL-CED1Z RoHS Compliant Part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CED1Z for evaluation/demonstration purposes. 3 This board allows the PC to control and communicate with all Analog Devices evaluation boards with model numbers ending with the ED designator. ...
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... NOTES Rev Page AD7625 ...
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... AD7625 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07652-0-1/09(0) Rev Page ...