AD7156 Analog Devices, AD7156 Datasheet - Page 5

• Manufacturer Part Number: AD7156
• Manufacturer: Analog Devices

Specifications of AD7156

• Resolution (bits): 12bit
• # Chan: 2
• Sample Rate: 100SPS
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Capacitive
• Ain Range: 0.5 pF,1 pF,2 pF,4 pF
• Pkg Type: CSP

TIMING SPECIFICATIONS
V
Table 2.
Parameter
CONVERTER
SERIAL INTERFACE
1
2
3
4
5
6
7
Conversion time is 304 internal clock cycles for both channels (nominal clock 16 kHz); the internal clock frequency is equal to the specified excitation frequency.
Specification is not production tested but is supported by characterization data at initial product release.
Wake-up time is the maximum delay between the last SCL edge writing the configuration register and the start of conversion.
Power-up time is the maximum delay between the V
interface command.
Reset time is the maximum delay between the last SCL edge writing the reset command and either the start of conversion or when ready to receive a serial
interface command.
Sample tested during initial release to ensure compliance.
All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
DD
Conversion Time
Wake-Up Time from Power-Down Mode
SCL Frequency
SCL High Pulse Width, t
SCL Low Pulse Width, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Hold Time (Start Condition), t
Setup Time (Start Condition), t
Data Setup Time, t
Setup Time (Stop Condition), t
Data Hold Time (Master), t
Bus-Free Time (Between Stop and Start Conditions), t
Power-Up Time
Reset Time
= 1.8 V to 3.6 V, GND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = V
SDA
SCL
2, 5
2, 4
6, 7
P
1
t
BUF
SU;DAT
F
R
S
LOW
HIGH
t
HD;STA
HD;DAT
HD;STA
SU;STO
SU;STA
t
LOW
t
R
t
HD;DAT
2, 3
DD
crossing the minimum level (1.8 V) and either the start of conversion or when ready to receive a serial
Figure 2. Serial Interface Timing Diagram
t
BUF
HIGH
t
F
t
SU;DAT
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Min
0
0.6
1.3
0.6
0.6
0.1
0.6
10
1.3
Typ
0.3
2
2
DD
, temperature range = −40°C to +85°C, unless otherwise noted.
Max
20
400
0.3
0.3
S
t
SU;STA
Unit
ms
ms
ms
ms
kHz
μs
μs
μs
μs
μs
μs
μs
μs
ns
μs
t
HD;STA
Test Conditions/Comments
Both channels, 10 ms per channel.
See Figure 2.
After this period, the first clock is generated.
Relevant for repeated start condition.
t
SU;STO
P
AD7156