AD7190 Analog Devices, AD7190 Datasheet
AD7190
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AD7190 Summary of contents
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... Data acquisition Medical and scientific instrumentation GENERAL DESCRIPTION The AD7190 is a low noise, complete analog front end for high precision measurement applications. It contains a low noise, 24-bit sigma-delta (∑-Δ) analog-to-digital converter (ADC). The on-chip low noise gain stage means that signals of small amplitude can be interfaced directly to the ADC ...
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... AD7190 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Characteristics ................................................................ 7 Circuit and Timing Diagrams ..................................................... 7 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configuration and Function Descriptions ........................... 10 Typical Performance Characteristics ........................................... 12 RMS Noise and Resolution ............................................................ 15 4 Sinc Chop Disabled ................................................................... 15 ...
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... Hz output data rate, 50 ± 1 Hz, 60 ± 1 Hz. dB min 50 Hz output data rate, REJ60 50 ± 1 Hz, 60 ± 1 Hz. dB min 50 Hz output data rate, 50 ± 1 Hz. dB min 60 Hz output data rate, 60 ± 1 Hz. Rev Page AD7190 1 4 filter. 3 filter. 4 filter 3 . ...
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... AD7190 Parameter AD7190B External Clock @ 50 Hz 120 120 @ 60 Hz 120 3 Sinc Filter Internal Clock @ 50 Hz External Clock @ 50 Hz 100 ANALOG INPUTS Differential Input Voltage Ranges ±V ±(AV 2 Absolute AIN Voltage Limits Unbuffered Mode AGND − ...
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... V min DD V max V min V max μA max pF typ V max V min V min V max Rev Page AD7190 1 Test Conditions/Comments Applies after user calibration at 25°C. Bipolar mode. Continuous current. Analog inputs must be buffered and chop disabled 5V 200 μA. DD SOURCE 800 μ ...
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... AD7190 Parameter AD7190B 8 POWER REQUIREMENTS Power Supply Voltage AV − AGND 4.75/5. − DGND 2.7/5.25 DD Power Supply Currents AI Current 1 DD 1.3 4.5 4.75 6.2 6.75 DI Current 0.4 DD 0.6 1.5 I (Power-Down Mode Temperature range −40° +105°C. MIN MAX 2 Specification is not production tested but is supported by characterization data at initial product release. ...
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... WITH DV SOURCE 100µA WITH DV = 3V) DD Figure 2. Load Circuit for Timing Characterization Rev Page unless (10 and timed from a voltage level of 1 limits 5V 5V, DD AD7190 4 ...
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... AD7190 DOUT/RDY (O) SCLK (I) SCLK ( MSB INPUT OUTPUT Figure 3. Read Cycle Timing Diagram CS ( DIN (I) MSB LSB I = INPUT OUTPUT Figure 4. Write Cycle Timing Diagram Rev Page LSB ...
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... THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device JA soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type 24-Lead TSSOP + 0 ESD CAUTION + Rev Page AD7190 θ θ Unit JA JC 128 42 °C/W ...
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... Master Clock Signal for the Device. The AD7190 has an internal 4.92 MHz clock. This internal clock can be made available on the MCLK2 pin. The clock for the AD7190 can be provided externally also in the form of a crystal or external clock. A crystal can be tied across the MCLK1 and MCLK2 pins. Alternatively, the MCLK2 pin can be driven with a CMOS-compatible clock and the MCLK1 pin left unconnected ...
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... Logic input that allows for synchronization of the digital filters and analog modulators when using multiple AD7190 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset and the analog modulator is held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state low ...
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... AD7190 TYPICAL PERFORMANCE CHARACTERISTICS 8,388,760 8,388,758 8,388,756 8,388,754 8,388,752 8,388,750 8,388,748 8,388,746 0 200 400 600 SAMPLE Figure 6. Noise ( Output Data Rate = 4.7 Hz, Gain = 128, Chop REF 4 Disabled, Sinc Filter) 250 200 150 100 50 0 CODE Figure 7. Noise Distribution Histogram (V Output Data Rate = 4.7 Hz, Gain = 128, Chop Disabled, Sinc ...
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... V, REF 4 Filter) Rev Page AD7190 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 V (V) IN Figure 12. INL (Gain = 1) 0 0.005 0.010 0.015 V (V) IN Figure 13 ...
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... AD7190 –60 –40 – TEMPERATURE (°C) Figure 14. Offset Error (Gain = 1, Chop Disabled) 0 –0.1 –0.2 –0.3 –0.4 –0.5 –0.6 –0.7 –60 –40 – TEMERATURE (°C) Figure 15. Offset Error (Gain = 128, Chop Disabled) 1.000008 1.000007 1.000006 1.000005 1 ...
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... RMS NOISE AND RESOLUTION The AD7190 has a choice of two filter types: sinc In addition, the AD7190 can be operated with chop enabled or chop disabled. The following tables show the rms noise of the AD7190 for some of the output data rates and gain settings with chop disabled 4 3 ...
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... AD7190 3 SINC CHOP DISABLED Table 8. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 4.7 639.4 640 7.5 400 480 10 300 150 20 16 300 10 5 960 3.125 2 2400 1.25 1 4800 0.625 Table 9. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate ...
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... Rev Page AD7190 Gain of 32 Gain of 64 Gain of 128 8 11.5 8 124 99 86 198 156 140 ...
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... AD7190 3 SINC CHOP ENABLED Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) 1023 1.56 1282 640 2.5 800 480 3.33 600 96 16.6 120 80 20 100 100 20 5 320 6.25 2 800 2.5 1 1600 1.25 Table 13. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate ...
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... CR denoting that the bits are in the communications register. CR7 denotes the first bit of the data stream. The number in parentheses indicates the power-on/reset default status of that bit. CR4 CR3 CR2 RS1(0) RS0(0) CREAD(0) Rev Page AD7190 CR1 CR0 0(0) 0(0) Register Size 8 bits 8 bits 24 bits 24 bits 24 bits/32 bits ...
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... AD7190 STATUS REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x80) The status register is an 8-bit, read-only register. To access the ADC status register, the user must write to the communications register, select the next operation read, and load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 16 outlines the bit designations for the status register ...
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... MR19 to MR18 CLK1 to CLK0 These bits are used to select the clock source for the AD7190. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7190 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7190 ...
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... Power-down mode. In power-down mode, all AD7190 circuitry, except the bridge power-down switch, is powered down. The bridge power-down switch remains active because the user may need to power up the sensor prior to powering up the AD7190 for settling reasons. The external crystal, if selected, remains active. ...
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... These bits must be programmed with a Logic 0 for correct operation. CON15 to CON8 CH7 to CH0 Channel select bits. These bits are used to select which channels are enabled on the AD7190. See Table 20. Several channels can be selected, and the AD7190 automatically sequences them. The conversion on each channel requires the complete settling time. ...
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... AIN3 AIN4 ID REGISTER RS2, RS1, RS0 = Power-On/Reset = 0xX4 The identification number for the AD7190 is stored in the ID register. This is a read-only register. GPOCON REGISTER (RS2, RS1, RS0 = Power-On/Reset = 0x00) The GPOCON register is an 8-bit register from which data can be read or to which data can be written ...
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... RS1, RS0 = Power-On/Reset = 0x5XXXX0) The full-scale register is a 24-bit register that holds the full-scale calibration coefficient for the ADC. The AD7190 has four full- scale registers; therefore, each channel has a dedicated full-scale register. The full-scale registers are read/write registers. However, when writing to the full-scale registers, the ADC must be placed in power-down mode or idle mode ...
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... IN+ OUT+ OUT– IN– OVERVIEW The AD7190 is an ultralow noise ADC that incorporates a ∑-Δ modulator, a buffer, PGA, and on-chip digital filtering intended for the measurement of wide dynamic range signals such as those in pressure transducers, weigh scales, and strain gauge applications. The part can be configured to have two differential inputs or four pseudo differential inputs that can be buffered or unbuffered ...
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... FREQUENCY (Hz) 4 Filter Response (Output Data Rate = 12.5 Hz, Chop Enabled) 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 100 FREQUENCY (Hz) 3 Filter Response (Output Data Rate = 16.6 Hz, Chop Enabled) AD7190 4 filter is 3dB 4 125 150 125 150 ...
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... For example, when zero latency is not enabled, the AD7190 has a noise-free resolution of 18.5 bits when the output data rate and the gain is set to 128. When zero latency is enabled, the ADC has a resolution of 17 ...
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... The serial interface of the AD7190 consists of four signals DIN, SCLK, and DOUT/ RDY . The DIN line is used to transfer data into the on-chip registers, whereas DOUT/ RDY is used for accessing data from the on-chip registers ...
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... The serial interface can be reset by writing a series the DIN input Logic 1 is written to the AD7190 DIN line for at least 40 serial clock cycles, the serial interface is reset. This ensures that the interface can be reset to a known state if the interface gets lost due to a software error or some glitch in the system ...
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... Continuous Conversion Mode Continuous conversion is the default power-up mode. The AD7190 converts continuously, the RDY bit in the status register going low each time a conversion is complete low, the DOUT/ RDY line also goes low when a conversion is completed. To read a conversion, the user writes to the com- munications register, indicating that the next operation is a read of the data register ...
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... Also, the user must ensure that the data-word is read before the next conversion is complete. If the user has not read the conversion before the completion of the next conversion insufficient serial clocks are applied to the AD7190 to read the word, the serial output register is reset when the next CS ...
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... Hz, which is equivalent to 23 bits of effective resolution or 20.5 bits of noise-free resolution. The AD7190 can be programmed to have a gain 16, 32, 64, and 128 using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the unipolar ranges are from 19. 2.5 V, and the bipolar ranges are from ± ...
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... REFINx(–) pins is between 0.3 V and 0.6 V, the AD7190 detects that it no longer has a valid reference. In this case, the NOREF bit of the status register is set the AD7190 is performing normal conversions and the NOREF bit becomes active, the conversion result is all 1s. Therefore not necessary to continuously monitor the status of the NOREF bit when performing conversions ...
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... AD7190 into a consistent, known state. While the SYNC pin is low, the AD7190 is maintained in this state. On the SYNC rising edge, the modulator and filter are taken out of this reset state and, on the next clock edge, the part starts to gather input samples again. ...
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... The gain error of the AD7190 is factory calibrated at a gain of 1 with power supply at ambient temperature. Following this calibration, the gain error is 0.001%, typically Table 23 shows the typical uncalibrated gain error for the different gain settings ...
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... AD7190 to prevent noise coupling. The power supply lines to the AD7190 must use as wide a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Shield fast switching signals ...
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... WEIGH SCALES Figure 32 shows the AD7190 being used in a weigh scale application. The load cell is arranged in a bridge network and gives a differential output voltage between its OUT+ and OUT– terminals. Assuming excitation voltage, the full-scale output range from the transducer when the sensitivity is 2 mV/V ...
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... BSC 1 12 PIN 1 0.65 1.20 BSC MAX 0.30 0.20 SEATING 0.19 PLANE 0.09 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153-AD Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters Package Description 24-Lead TSSOP 24-Lead TSSOP Evaluation Board Rev Page 8° 0.75 0° 0.60 0.45 Package Option RU-24 RU-24 AD7190 ...
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... AD7190 NOTES ©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07640-0-5/09(B) Rev Page ...