AD7991 Analog Devices, AD7991 Datasheet - Page 17

• Manufacturer Part Number: AD7991
• Description: 4-Channel, 12-Bit ADC with I2C Compatible Interface in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7991

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 140kSPS
• Interface: I²C/Ser 2-Wire
• Analog Input Type: SE-Uni
• Ain Range: Uni (Vref),Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

THEORY OF OPERATION
The AD7991/AD7995/AD7999 are low power, 12-/10-/8-bit,
single-supply, 4-channel ADCs. Each part can be operated from
a single 2.35 V to 5.5 V supply.
The AD7991/AD7995/AD7999 provide the user with a 4-channel
multiplexer, an on-chip track-and-hold, an ADC, and an I
compatible serial interface, all housed in an 8-lead SOT-23 package
that offers the user considerable space-saving advantages over
alternative solutions.
The AD7991/AD7995/AD7999 normally remains in a power-
down state while not converting. Therefore, when supplies are
first applied, the part is in a power-down state. Power-up is initiated
prior to a conversion, and the device returns to the power-down
state upon completion of the conversion. This automatic power-
down feature allows the device to save power between conversions.
This means any read or write operations across the I
can occur while the device is in power-down.
CONVERTER OPERATION
The AD7991/AD7995/AD7999 are successive approximation
ADCs built around a capacitive DAC. Figure 18 and Figure 19
show simplified schematics of the ADC during its acquisition
and conversion phases, respectively. Figure 18 shows the ADC
during its acquisition phase: SW2 is closed, SW1 is in Position A,
the comparator is held in a balanced condition, and the sampling
capacitor acquires the signal on V
analog input needs to settle the analog input signal to within
one LSB in 0.6 μs, which is equivalent to the duration of the
power-up and acquisition time.
AGND
V
IN
A
SW1
B
Figure 18. ADC Acquisition Phase
SW2
IN
. The source driving the
COMPARATOR
CAPACITIVE
CONTROL
2
LOGIC
C interface
DAC
2
C-
Rev. B | Page 17 of 28
When the ADC starts a conversion, as shown in Figure 19, SW2
opens and SW1 moves to Position B, causing the comparator to
become unbalanced. The input is disconnected when the con-
version begins. The control logic and the capacitive DAC are used
to add and subtract fixed amounts of charge from the sampling
capacitor to bring the comparator back into a balanced condition.
When the comparator is rebalanced, the conversion is complete.
The control logic generates the ADC output code. Figure 20 shows
the ADC transfer function.
ADC Transfer Function
The output coding of the AD7991/AD7995/AD7999 is straight
binary. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size for
the AD7991/AD7995/AD7999 is V
V
characteristics for the AD7991/AD7995/AD7999.
AGND
REF
V
IN
/256, respectively. Figure 20 shows the ideal transfer
Figure 20. AD7991/AD7995/AD7999 Transfer Characteristics
SW1
A
111 ... 111
111 ... 110
111 ... 000
011 ... 111
000 ... 010
000 ... 001
000 ... 000
B
Figure 19. ADC Conversion Phase
AGND + 1 LSB
AD7991/AD7995/AD7999
SW2
ANALOG INPUT
AD7991 1 LSB = REF
AD7995 1 LSB = REF
AD7999 1 LSB = REF
0V TO REF
REF
COMPARATOR
/4096, V
+REF
IN
IN
– 1 LSB
REF
IN
IN
IN
/1024, and
CAPACITIVE
/4096
/1024
/256
CONTROL
LOGIC
DAC