AD9626 Analog Devices, AD9626 Datasheet
AD9626
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AD9626 Summary of contents
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... CMOS compatible and support either twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9626 is available in a 56-lead LFCSP, specified over the industrial temperature range (−40°C to +85°C). ...
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... Digital Outputs ........................................................................... 20 Timing—Single Port Mode ....................................................... 21 Timing—Interleaved Mode....................................................... 21 Layout Considerations................................................................... 22 Power and Ground Recommendations ................................... 22 CML ............................................................................................. 22 RBIAS........................................................................................... 22 AD9626 Configuration Using the SPI ..................................... 22 Hardware Interface..................................................................... 23 Configuration Without the SPI ................................................ 23 Memory Map .................................................................................. 25 Reading the Memory Map Table.............................................. 25 Reserved Locations .................................................................... 25 Default Values ............................................................................. 25 Logic Levels................................................................................. 25 Evaluation Board ...
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... MHz sine input at rated sample rate. AVDD DRVDD 4 Single data rate mode; this is the default mode of the AD9626. 5 Interleaved mode; user-programmable feature. See the Memory Map section. = +85° −1.0 dBFS, full scale = 1.25 V, single port output mode, DCS enabled, ...
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... Full 63.0 25°C 64.5 Full 63.5 25°C 64.2 Full 62.6 25°C 10.6 25°C 10.5 25°C 84 Full 75 25°C 79 Full 71 25°C 92 Full 85 25°C 92 Full 81 25°C 80 25°C 25°C 700 Rev Page AD9626-210 AD9626-250 Typ Max Min Typ Max 64.4 64.0 63.0 64.2 63.8 62.3 64.4 64.0 62.8 64.0 63.4 62.0 10.6 10.5 10.5 10 ...
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... Max CMOS/LVDS/LVPECL 1.2 1.2 6 0.2 6 AVDD + AVDD − AVDD + 1.6 0.3 1.6 AVDD 1.1 AVDD 3.6 1.2 3.6 0 0.8 × AVDD 0.2 × 0.2 × AVDD AVDD 0 0 −60 − DRVDD − 0.05 GND + 0.05 GND + 0.05 AD9626 Unit kΩ μA μA μA μ ...
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... Full 170 210 Full 40 Full 2.65 2.9 2.15 Full 2.65 2.9 2.15 25°C 3.7 25°C 3.4 Full 0 0.3 0.55 0 Full 6 25°C 3.5 25°C 3.0 Full 0 0.5 1.1 0 Full 6 25°C 250 50 25°C 0.1 25°C 0.2 Rev Page AD9626-210 AD9626-250 Typ Max Min Typ Max 250 40 40 2.4 1.8 2.0 2.4 1.8 2.0 3.7 3.7 3.4 3.4 0.3 0.55 0 0.3 0. 3.5 3.5 3.0 3.0 0.5 1.1 0 0.5 1 250 250 50 50 0.1 0.1 0.2 ...
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... CLK t t CPDA CPDB t SKEWA N – – – SKEWB t PDB N – – 3 Figure 3. Interleaved Mode Rev Page – – AD9626 ...
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... AD9626 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD Dx0 Through Dx11 to DRGND DCO+/DCO− to DRGND OVRA/OVRB to DGND CLK+ to AGND CLK− to AGND VIN+ to AGND VIN− to AGND SDIO/DCS to DGND PDWN to AGND CSB to AGND ...
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... Output Port A Output Bit 1. Output Port A Output Bit 2. Output Port A Output Bit 3. Output Port A Output Bit 4. Output Port A Output Bit 5. Output Port A Output Bit 6. Output Port A Output Bit 7. Rev Page AD9626 42 AVDD 41 AVDD 40 CML 39 AVDD 38 AVDD 37 AVDD 36 VIN– 35 VIN+ ...
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... AD9626 Pin No. Mnemonic 3 DA8 4 DA9 5 DA10 6 DA11 (MSB) 9 OVRA 10 DB0 (LSB) 11 DB1 12 DB2 13 DB3 14 DB4 15 DB5 16 DB6 17 DB7 18 DB8 19 DB9 20 DB10 21 DB11 (MSB) 22 OVRB 1 AGND and DRGND should be tied to a common quiet ground plane. Description Output Port A Output Bit 8. Output Port A Output Bit 9. ...
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... Figure 7. Equivalent SCLK/DFS, RESET, PDWN Input Circuit CLK– AVDD V CML ~1.4V = ~1.4 V) Rev Page AVDD 26kΩ 1kΩ CSB Figure 8. Equivalent CSB Input Circuit DRVDD DRGND Figure 9. CMOS Outputs (Dx, OVRA, OVRB, DCO+, DCO−) DRVDD 1kΩ SDIO/DCS Figure 10. Equivalent SDIO/DCS Input Circuit AD9626 ...
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... SNR: 64.4dB ENOB: 10.5 BITS SFDR: 79dBFS –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 12. AD9626-170 64k Point Single-Tone FFT; 170 MSPS, 70.3 MHz 0 –20 –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 13. AD9626-170 64k Point Single-Tone FFT; 170 MSPS, 140.3 MHz = 25° ...
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... Figure 20. SNR/SFDR vs. Analog Input Frequency, Interleaved Mode vs. 0 –20 –40 –60 –80 –100 –120 –140 245 0 Figure 21. AD9626-210 64k Point Single-Tone FFT; 210 MSPS, 10.3 MHz 0 210MSPS 70.3MHz @ –1.0dBFS –20 SNR: 64.2dB ENOB: 10.5 BITS SFDR: 79dBc –40 –60 –80 –100 –120 – ...
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... Figure 25. AD9626-210 Single-Tone SNR/SFDR vs. Input Frequency (f and Temperature with 1.25 V p-p Full Scale; 210 MSPS 210MSPS 170.3MHz @ –1.0dBFS SNR: 63.23dB ENOB: 10.4 BITS SFDR: 78dBc 80 100 Figure 26. AD9626-210 SNR/SFDR vs. Input Amplitude; 210 MSPS, 170.3 MHz SNR (+25°C) 350 400 450 500 ) IN Rev Page ...
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... SFDR: 80dBc –40 –60 –80 –100 –120 –140 FREQUENCY (MHz) Figure 31. AD9626-250 64k Point Single-Tone FFT; 250 MSPS, 70.3 MHz –20 –40 –60 –80 –100 –120 –140 3072 3584 4096 Figure 32. AD9626-250 64k Point Single-Tone FFT; 250 MSPS, 170.3 MHz 35k ...
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... SFDR (dBFS SNR (dBFS SFDR (dBc) 30 SNR (dB AMPLITUDE (–dBFS) Figure 35. AD9626-250 SNR/SFDR vs. Input Amplitude; 250 MSPS, 170.3 MHz 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 512 1024 1536 2048 2560 OUTPUT CODE Figure 36. AD9626-250 INL; 250 MSPS ...
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... AD9626-250 5.0 4.5 AD9626-210 4.0 AD9626-170 3.5 3.0 2.5 2.0 –40 –30 –20 – TEMPERATURE (°C) Figure 41. Offset vs. Temperature Rev Page AD9626 ...
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... During power- down, the output buffers go into a high impedance state. ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9626 is a differential buffer. For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched such that common-mode settling errors are symmetrical ...
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... This allows a wide range of clock input duty cycles without affecting the performance of the AD9626. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS 0.1µ ...
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... ANALOG INPUT FREQUENCY (MHz) Figure 50. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS input Signal POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 37, the power dissipated by the AD9626 is proportional to its sample rate. The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers ...
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... S SKEW f /2 Spurious S Because the AD9626 output data rate is at one-half the sampling frequency in interleaved output mode, there is significant f energy in the outputs of the part, and there will be significant energy in the ADC output spectrum certain that this f /2 energy does not couple into either the S clock circuit or the analog inputs of the AD9626 ...
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... The CML pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 54. RBIAS The AD9626 requires the user to place a 10 kΩ resistor between the RBIAS pin and ground. This resistor sets the master current reference of the ADC core and should have at least a 1% tolerance. ...
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... The pins described in Table 8 comprise the physical interface between the user’s programming device and the serial port of the AD9626. All serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 kΩ). ...
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... AD9626 Table 10. Serial Timing Definitions Parameter Timing (minimum, ns CLK EN_SDIO t 5 DIS_SDIO Table 11. Output Data Format Input (V) Condition (V) VIN+ − VIN− < 0.62 VIN+ − VIN− = 0.62 VIN+ − VIN− ...
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... Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit. ” Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID, Bits[7:0] AD9626 = 0x3c 0 Speed grade 170 MSPS 01 = 210 MSPS 10 = 250 MSPS ...
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... AD9626 Addr Bit 7 (Hex) Parameter Name (MSB) Bit 6 09 clock test_io OF ain_config output_mode output_phase Output 0 clock polarity 1 = inverted 0 = normal (default) 17 flex_output_delay Output delay enable enable 1 = disable 18 flex_vref Bit 5 Bit 4 Bit 3 Bit Reset Reset Output test mode: ...
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... CMLX 33 33 optional R16 C21 0.1UF 10K R12 PRI SEC ETC1-1-13 Figure 54. AD9601 Evaluation Board Schematic Page 1 Rev Page 07099-053 GND GND GND DRVDD AVDD AVDD CR2 CR3 1 0.1UF C75 3 2 0.1UF C15 AD9626 ...
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... AD9626 100PF 0.1UF C71 C73 0.1UF 0.1UF C72 C70 0.1UF 0.1UF C69 C65 0.1UF C68 0.1UF 0.1UF C64 C67 0.1UF 0.1UF C63 C66 0.1UF 0.1UF C62 C13 0.1UF 0.1UF C27 C59 0.1UF C28 0.1UF C60 0.1UF C29 0.1UF C30 0.1UF 0.1UF ...
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... R67 R69 R71 R73 R64 R66 R68 R70 R72 R74 33 GND_PAD 31 GND 32 RSET DNP C49 DNP R49 Rev Page AD9626 07099-055 R75 R77 R79 R81 R83 R84 R76 R78 R80 R82 S10 S0 ...
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... AD9626 Table 13. Bill of Materials Reference Qty Designator Package 1 PCB 7 C1, C3, C4, C5, 603 C6, C7, C10 6 C8, C9, C11, 6032-28 C12, C14, C55 1 C17 402 7 C27, C32, C33, 402 C62, C63, C64, C71 6 C28, C29, C30, 402 C31, C65, C70 10 C21, C22, C23, 402 ...
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... Capacitor, 0.1 μF, ceramic, 10% LED green, USS type 0603 Schottky diode Connector, header, 0.1" TSW-110-08-G-D Connector, PCB coax SMA end launch, Johnson 142 Inductor SMA Rev Page AD9626 Vendor Part Number Panasonic ERJ-2GEJ360X Panasonic ERJ-2RKF15R0X NIC Components NRC04F1001TRF NIC Components ...
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... AD9626 Reference Qty Designator Package 0 R3, R14, R33, 402 R34, R35, R48, R49 0 R42, R43, R54, 402 R85, R86 0 R28, R29, R30, 402 R31, R32 0 R37, R38 402 0 R39, R45 402 0 R58, R59 402 0 R60, R61 402 0 R8, R9, R17, 402 R36, R40, R41, ...
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... Body, Very Thin Quad (CP-56-2) Dimensions shown in millimeters Package Description 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CMOS Evaluation Board with AD9626BCPZ-250 Rev Page 0.30 0.23 0.18 PIN 1 56 ...
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... AD9626 NOTES Rev Page ...
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... NOTES Rev Page AD9626 ...
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... AD9626 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07099-0-11/07(0) Rev Page ...