AD7982 Analog Devices, AD7982 Datasheet
AD7982
Specifications of AD7982
Available stocks
Related parts for AD7982
AD7982 Summary of contents
Page 1
... SDI input, to daisy-chain several ADCs on a single 3-wire bus and provides an optional busy indicator compatible with 1 and 5 V logic, using the separate VIO supply. The AD7982 is available in a 10-lead MSOP or a 10-lead QFN (LFCSP) with operation specified from −40°C to +85°C. 250 kSPS ...
Page 2
... CS Mode, 3-Wire Without Busy Indicator ............................. 17 CS Mode, 3-Wire with Busy Indicator .................................... 18 CS Mode, 4-Wire Without Busy Indicator ............................. 19 CS Mode, 4-Wire with Busy Indicator .................................... 20 Chain Mode Without Busy Indicator ...................................... 21 Chain Mode with Busy Indicator............................................. 22 Application Hints ........................................................................... 23 Layout .......................................................................................... 23 Evaluating AD7982 Performance............................................. 23 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24 Rev Page ...
Page 3
... See the Analog Inputs section 18 −0.85 ±0.5 +1.5 −2 ±1 +2 1.05 −0.023 +0.004 +0.023 ±1 ±100 +700 0 290 129 95.5 98 92.5 −115 −120 97 AD7982 Unit Bits Bits 1 LSB 1 LSB 1 LSB % of FS ppm/°C μV ppm/°C dB MSPS ...
Page 4
... AD7982 VDD = 2.5 V, VIO = 2 5.5 V, REF = Table 3. Parameter REFERENCE Voltage Range Load Current SAMPLING DYNAMICS −3 dB Input Bandwidth Aperture Delay DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format Pipeline Delay POWER SUPPLIES VDD ...
Page 5
... HSDISCK t 15 DSDOSDI 1 Y% VIO 1 t DELAY AND MAXIMUM V USED. SEE DIGITAL INPUTS IH IL Figure 3. Voltage Levels for Timing AD7982 Unit ...
Page 6
... AD7982 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs 1 IN+, IN− to GND Supply Voltage REF, VIO to GND VDD to GND VDD to VIO Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature θ Thermal Impedance JA 10-Lead MSOP 10-Lead QFN (LFCSP_WD) θ Thermal Impedance ...
Page 7
... AI = analog input digital input digital output, and P = power. VIO SDI SCK SDO CNV Rev Page AD7982 REF 1 10 VIO VDD 2 9 SDI AD7982 IN SCK TOP VIEW IN– SDO GND 5 6 CNV Figure 5. 10-Lead QFN (LFCSP) Pin Configuration ...
Page 8
... AD7982 TERMINOLOGY Integral Nonlinearity Error (INL) INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition ...
Page 9
... CODE IN HEX Figure 10. Histogram Input at the Code Transition 100 –10 –9 –8 –7 –6 –5 –4 –3 INPUT LEVEL (dB) Figure 11. SNR vs. Input Level AD7982 262144 222 –2 –1 0 ...
Page 10
... AD7982 100 SNR, SINAD 95 90 ENOB 85 80 2.25 2.75 3.25 3.75 4.25 REFERENCE VOLTAGE (V) Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage 100 –55 –35 – TEMPERATURE (°C) Figure 13. SNR vs. Temperature 100 0 FREQUENCY (kHz) Figure 14. SINAD vs. Frequency 18 –100 –105 17 –110 16 –115 – ...
Page 11
... VDD VIO –55 –35 – TEMPERATURE (°C) Figure 19. Power-Down Currents vs. Temperature 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.625 –55 –35 Figure 20. Operating Currents vs. Temperature 105 125 Rev Page AD7982 I VDD I REF I VIO – 105 125 TEMPERATURE (°C) ...
Page 12
... The AD7982 can be interfaced to any 1 digital logic family available in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that allows space savings and flexible configurations. ...
Page 13
... Transfer Functions The ideal transfer characteristic for the AD7982 is shown in Figure 22 and Table 7. 011...111 011...110 011...101 100...010 100...001 100...000 –FSR –FSR + 1 LSB –FSR + 0.5 LSB +FSR – 1.5 LSB ANALOG INPUT Figure 22. ADC Ideal Transfer Function VREF V– ...
Page 14
... AD7982. The noise from the driver is filtered by the AD7982 analog input circuit’s 1-pole, low- pass filter made by R and the external filter one is used. Because the typical noise of the AD7982 is 40 μV rms, the SNR degradation due to the amplifier is ⎛ ⎜ ⎜ ...
Page 15
... REF and GND pins. POWER SUPPLY The AD7982 uses two power supply pins: a core supply (VDD) and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and 5 reduce the number of supplies needed, VIO and VDD can be tied together ...
Page 16
... SDI hold time is such that when SDI and CNV are connected together, the chain mode is always selected. In either mode, the AD7982 offers the option of forcing a start bit in front of the data bits. This start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading ...
Page 17
... CS MODE, 3-WIRE WITHOUT BUSY INDICATOR This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host. The connection diagram is shown in Figure 29, and the corresponding timing is given in Figure 30. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
Page 18
... AD7982 CS MODE, 3-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host having an interrupt input. The connection diagram is shown in Figure 31, and the corresponding timing is given in Figure 32. With SDI tied to VIO, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance ...
Page 19
... CS MODE, 4-WIRE WITHOUT BUSY INDICATOR This mode is usually used when multiple AD7982s are connected to an SPI-compatible digital host. A connection diagram example using two AD7982s is shown in Figure 33, and the corresponding timing is given in Figure 34. With SDI high, a rising edge on CNV initiates a conversion, selects the CS mode, and forces SDO to high impedance. In this mode, CNV must be held high during the conversion phase and the subsequent data readback ...
Page 20
... AD7982 CS MODE, 4-WIRE WITH BUSY INDICATOR This mode is usually used when a single AD7982 is connected to an SPI-compatible digital host with an interrupt input and when it is desired to keep CNV, which is used to sample the analog input, independent of the signal used to select the data reading. This independence is particularly important in applications where low jitter on CNV is desired ...
Page 21
... CHAIN MODE WITHOUT BUSY INDICATOR This mode can be used to daisy-chain multiple AD7982s on a 3-wire serial interface. This feature is useful for reducing component count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited interfacing capacity. Data readback is analogous to clocking a shift register. ...
Page 22
... When all ADCs in the chain have completed their conversions, the SDO pin of the ADC closest to the digital host (see the AD7982 ADC labeled C in Figure 39) is driven high. This transition on SDO can be used as a busy indicator to trigger the data readback controlled by the digital host. The AD7982 then enters the acquisition phase and powers down ...
Page 23
... The pinout of the AD7982, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7982 is used as a shield ...
Page 24
... AD7982BCPZ −40°C to +85°C AD7982BCPZ-RL7 1 −40°C to +85°C 1 AD7982BCPZ-RL −40°C to +85° EVAL-AD7982CBZ 3 EVAL-CONTROL BRD3Z RoHS compliant part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. ...