AD7951 Analog Devices, AD7951 Datasheet
AD7951
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AD7951 Summary of contents
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... The device is configured through hardware or via a dedicated write only serial configuration port for input range and operating mode. The AD7951 contains a high speed 14-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports ...
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... AD7951 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 12 Terminology .................................................................................... 16 Theory of Operation ...................................................................... 17 Overview...................................................................................... 17 Converter Operation.................................................................. 17 Modes of Operation ................................................................... 18 Transfer Functions...................................................................... 18 Typical Connection Diagram ................................................... 19 Analog Inputs ...
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... Full-scale step PDREF = PDBUF = low REF @ 25°C –40°C to +85°C AVDD = 5 V ± 5% 1000 hours μF REF Rev Page AD7951 unless otherwise noted. MIN MAX Min Typ Max 14 −0.1 +5.1 −0.1 +10.1 −5.1 +5.1 − ...
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... AD7951 Parameter REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format 5 Pipeline Delay POWER SUPPLIES Specified Performance ...
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... Rev Page AD7951 unless otherwise noted. MIN MAX Typ Max Unit ns μ 850/1100/1350 850/1100/1350 850/1100/1350 ...
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... AD7951 Parameter SLAVE SERIAL/SERIAL CONFIGURATION INTERFACE MODES (See Figure 42, Figure 43, and Figure 45) External SDCLK, SCCLK Setup Time External SDCLK Active Edge to SDOUT Delay SDIN/SCIN Setup Time SDIN/SCIN Hold Time External SDCLK/SCCLK Period External SDCLK/SCCLK High External SDCLK/SCCLK Low 1 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION = 91°C/ 26°C/W. JA Rev Page AD7951 ...
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... EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally generated serial data clock that clocks the data output. In other serial modes, these pins are high impedance outputs AGND 1 PIN 1 AVDD 2 AGND 3 4 OB/2C 5 AD7951 WARP 6 TOP VIEW IMPULSE 7 (Not to Scale) SER/PAR ...
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... Serial Data output. In all serial modes this pin is used as the serial data output synchronized to SDCLK. Conversion results are stored in an on-chip register. The AD7951 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. ...
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... RESET DI Reset Input. When high, reset the AD7951. Current conversion, if any, is aborted. The falling edge of RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register. See the Digital Interface section. If not used, this pin can be tied to OGND. ...
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... AI = analog input; AI/O = bidirectional analog analog output digital input; DI/O = bidirectional digital digital output power serial configuration mode (SER/ PAR = high, HW low), this input is programmed with the serial configuration register and this pin is a don’t care. See the Hardware Configuration section and Software Configuration section. Rev Page AD7951 ...
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... AD7951 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = DVDD = 5 V; OVDD = 5 V; VCC = 15 V; VEE = − 1.0 0.5 0 –0.5 –1.0 0 4096 8192 CODE Figure 5. Integral Nonlinearity vs. Code 250 200 150 100 50 0 –1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 INL DISTRIBUTION (LSB) Figure 6. Integral Nonlinearity Distribution (239 Devices) ...
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... SNR SINAD –50 –40 –30 –20 –10 INPUT LEVEL (dB) 10 FREQUENCY (kHz) Figure 15. THD, Harmonics, and SFDR vs. Frequency 10V ±5V ±10V –35 – TEMPERATURE (°C) Figure 16. SINAD vs. Temperature AD7951 0 120 110 100 100 105 125 ...
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... AD7951 – 10V ±5V ±10V –100 –104 –108 –112 –116 –120 –55 –35 – TEMPERATURE (°C) Figure 17. THD vs. Temperature 1.5 ZERO ERROR POSITIVE FS ERROR 1.0 NEGATIVE FS ERROR 0.5 0 –0.5 –1.0 –1.5 –55 –35 – TEMPERATURE (°C) Figure 18. Zero Error, Positive and Negative Full Scale vs. Temperature ...
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... TEMPERATURE (°C) Figure 23. Power-Down Operating Currents vs. Temperature 105 Figure 24. Typical Delay vs. Load Capacitance C Rev Page AD7951 OVDD = 2.7V @ 85°C OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 50 100 150 200 C (pF ...
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... CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7951 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25° ...
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... The AD7951 is a very fast, low power, precise, 14-bit analog-to- digital converter (ADC) using successive approximation capacitive digital-to-analog (CDAC) converter architecture. The AD7951 can be configured at any time for one of four input ranges and conversion mode with inputs in parallel and serial hardware modes dedicated write only, SPI-compatible interface via a configuration register in serial software mode. The AD7951 uses Analog Devices’ ...
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... AD7951 ideal for battery-powered applications. TRANSFER FUNCTIONS Using the OB/ 2C digital input or via the configuration register, the AD7951 offers two output codings: straight binary and twos complement. See Figure 26 and Table 7 for the ideal transfer characteristic and digital output codes for the different analog input ranges, V register, the OB/ 2C input is a don’ ...
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... TYPICAL CONNECTION DIAGRAM Figure 27 shows a typical connection diagram for the AD7951 using the internal reference, serial data and serial configuration interfaces. Different circuitry from that shown in Figure 27 is optional and is discussed in the following sections. ANALOG SUPPLY (5V) 100nF 10µF +7V TO +15.75V SUPPLY 100nF 10µ ...
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... V range. During the conversion phase, when the switches are opened, the input impedance is limited to C Since the input impedance of the AD7951 is very high, it can be directly driven by a low impedance source without gain error. To further improve the noise filtering achieved by the AD7951 analog input circuit, an external, one-pole RC filter between the amplifier’ ...
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... N amp, in nV/√Hz. • The driver needs to have a THD performance suitable to that of the AD7951. Figure 15 shows the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs external compensation capacitor that should have good linearity as an NPO ceramic or mica type ...
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... The OVDD supplies the digital outputs and allows direct interface with any logic working between 2.3 V and 5.25 V. OVDD should be set to the same level as the system interface. Sufficient decoupling is required, consisting of at least a 10 μF capacitor and 100 nF with the 100 nF placed as close as possible to the AD7951. Rev Page TEMP ADG779 ...
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... PD input is a don’t care and should be tied to either high or low. CONVERSION CONTROL The AD7951 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 33. ...
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... RD is generally used to enable the conversion result on the data bus. RESET The RESET input is used to reset the AD7951. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET resets the AD7951 and clears the data bus and configuration register. See Figure 34 for the RESET timing details ...
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... Usually, because the AD7951 is used with a fast throughput, this mode is the HI-Z HIGH BYTE most recommended serial mode. In this mode, the serial clock and data toggle at appropriate instances, minimizing potential feedthrough between digital activity and critical conversion decisions ...
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... AD7951 CS CNVST BUSY t 29 SYNC t 14 SDCLK t 15 SDOUT t 16 CS, RD CNVST BUSY t 17 SYNC SDCLK t 18 SDOUT Figure 40. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) RDC/SDIN = 0 INVSCLK = INVSYNC = 0 EXT/INT = ...
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... EXT/ INT , INVSCLK, SDIN, SDOUT, SDCLK and RDERROR. External Clock (SER/ PAR = High, EXT/ INT = High) Setting the EXT/ INT = high allows the AD7951 to accept an externally supplied serial data clock on the SDCLK pin. In this mode, several methods can be used to read the data. The external serial clock is gated by CS ...
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... AD7951 External Clock Data Read After/During Conversion It is also possible to begin to read data after conversion and continue to read the last bits after a new conversion has been initiated. This method allows the full throughput and the use of a slower SDCLK frequency. Again recommended to use a ...
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... SOFTWARE CONFIGURATION The pins multiplexed on D[13:10] used for software configura- tion are: HW SCIN, SCCLK, and SCCS . The AD7951 is programmed using the dedicated write-only serial configurable port (SCP) for conversion mode, input range selection, output coding, and power-down using the serial configuration register. ...
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... Figure 46 shows an interface diagram between the AD7951 and the SPI-equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7951 acts as a slave device, and data must be read after conversion. This mode also allows the daisy-chain feature. The convert command could be initiated in response to an internal timer interrupt ...
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... Run traces on different but close layers of the board, at right angles to each other, to reduce the effect of feedthrough through the board. The power supply lines to the AD7951 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the impedance of the supplies presented to the AD7951, and to reduce the magnitude of the supply spikes ...
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... AD7951BCPZ −40°C to +85°C AD7951BCPZRL 1 −40°C to +85°C 1 AD7951BSTZ −40°C to +85°C 1 AD7951BSTZRL −40°C to +85°C 2 EVAL-AD7951CB 3 EVAL-CONTROL BRD3 Pb-free part. 2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. ...