AD9228 Analog Devices, AD9228 Datasheet
AD9228
Specifications of AD9228
Available stocks
Related parts for AD9228
AD9228 Summary of contents
Page 1
... The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI). The AD9228 is available in an RoHS compliant, 48-lead LFCSP specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1 ...
Page 2
... AD9228 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 AC Specifications .......................................................................... 5 Digital Specifications ................................................................... 6 Switching Specifications .............................................................. 7 Timing Diagrams .............................................................................. 8 Absolute Maximum Ratings .......................................................... 10 Thermal Impedance ................................................................... 10 ESD Caution ................................................................................ 10 Pin Configuration and Function Descriptions ........................... 11 Equivalent Circuits ......................................................................... 13 Typical Performance Characteristics ........................................... 15 Theory of Operation ...................................................................... 20 ...
Page 3
... Change to Input Signals Section ................................................... 36 Changes to Output Signals Section ............................................... 36 Changes to Figure 71 ...................................................................... 36 Changes to Default Operation and Jumper Selection Settings Section ........................................... 37 Changes to Alternative Analog Input Drive Configuration Section .................................................... 38 Changes to Figure 74 ...................................................................... 40 Changes to Table 17 ........................................................................ 48 Changes to Ordering Guide ........................................................... 52 4/06—Revision 0: Initial Version Rev Page AD9228 ...
Page 4
... Full 1.7 1.8 1.9 Full 155 170 Full 31 34 Full 335 367 Full 2 5.8 Full 72 Full −100 Full −100 Rev Page Data Sheet AD9228-65 Min Typ Max Unit 12 Bits Guaranteed ±1 ±8 mV ±2 ±8 mV ±2 ±3 ±0.3 ±0 ±0.3 ±0.65 LSB ±0.4 ±1 LSB ± ...
Page 5
... Full 72 82 Full 80 Full 80 Full −85 Full −82 −72 Full −80 Full −80 Full −90 Full −90 −80 Full −90 Full −90 25°C 80.8 25°C 75.0 Rev Page AD9228 AD9228-65 Min Typ Max Unit 70.2 dB 70.0 dB 68.5 70.0 dB 69.5 dB 70.0 dB 70.0 dB 68.0 69.8 dB 69.0 dB 11.37 Bits 11.33 Bits 11.1 11.33 Bits 11.25 Bits ...
Page 6
... Full 1.79 Full 0.05 LVDS Full 247 454 Full 1.125 1.375 Offset binary LVDS Full 150 250 Full 1.10 1.30 Offset binary Rev Page Data Sheet AD9228-65 Min Typ Max Unit CMOS/LVDS/LVPECL 250 mV p-p 1 kΩ 1.5 pF 1.2 3 kΩ 0.5 pF 1.2 3 kΩ ...
Page 7
... SAMPLE (t /24) − 300 (t /24) (t /24) + 300 SAMPLE SAMPLE SAMPLE (t /24) − 300 (t /24) (t /24) + 300 SAMPLE SAMPLE SAMPLE ±50 ±150 600 375 8 500 <1 2 AD9228 Unit MSPS MSPS μs CLK cycles ps ps rms CLK cycles ...
Page 8
... AD9228 TIMING DIAGRAMS N – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – – 1 VIN ± CLK– CLK+ t CPD DCO– DCO+ t FCO FCO– FCO – x ...
Page 9
... – – – – – – – 9 Figure 4. 12-Bit Data Serial Stream, LSB First Rev Page AD9228 D10 LSB D0 N – – – – – – ...
Page 10
... AD9228 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs DRGND ( − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− AGND VIN + x, VIN − x AGND SDIO/ODM AGND PDWN, SCLK/DTP, CSB ...
Page 11
... Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Chip Select Bar Power-Down Rev Page AD9228 AVDD 36 AVDD 35 VIN – VIN + A 33 AVDD ...
Page 12
... AD9228 Pin No. Mnemonic 33 VIN + A 34 VIN − VIN − VIN + B 40 RBIAS 41 SENSE 42 VREF 43 REFB 44 REFT 47 VIN + C 48 VIN − C Description ADC A Analog Input True ADC A Analog Input Complement ADC B Analog Input Complement ADC B Analog Input True External resistor sets the internal ADC core bias current ...
Page 13
... Figure 8. Equivalent SDIO/ODM Input Circuit 1.25V SCLK/DTP Rev Page DRVDD V V D– DRGND Figure 9. Equivalent Digital Output Circuit 1kΩ AND PDWN 30kΩ Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit 100Ω RBIAS Figure 11. Equivalent RBIAS Circuit AD9228 ...
Page 14
... AD9228 AVDD 70kΩ 1kΩ CSB Figure 12. Equivalent CSB Input Circuit 1kΩ SENSE Figure 13. Equivalent SENSE Circuit VREF Figure 14. Equivalent VREF Circuit Rev Page Data Sheet 6kΩ ...
Page 15
... FREQUENCY (MHz) = 120 MHz AIN = –0.5dBFS SNR = 67.68dB ENOB = 10.95 BITS –20 SFDR = 62.23dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) = 170 MHz AD9228 MSPS SAMPLE MSPS SAMPLE MSPS SAMPLE ...
Page 16
... AD9228 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 21. Single-Tone 32k FFT with f = 190 MHz –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 22. Single-Tone 32k FFT with f = 250 MHz p-p, SFDR p-p, SNR ...
Page 17
... IMD2 = 81.03dBc –20 IMD3 = 75.00dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 32. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE AD9228 2V p-p, SNR – MSPS SAMPLE MHz, IN2 MHz, IN2 ...
Page 18
... AD9228 0 AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 33. Two-Tone 32k FFT with MHz and f IN1 MSPS SAMPLE 0 AIN1 AND AIN2 = –7dBFS –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 34 ...
Page 19
... FREQUENCY (MHz) Figure 41. Noise Power Ratio (NPR MSPS SAMPLE 0 –1 –2 –3dB CUTOFF = 315MHz –3 –4 –5 –6 –7 –8 –9 – 100 150 200 250 300 350 FREQUENCY (MHz) AD9228 25 30 400 450 500 = 65 MSPS SAMPLE ...
Page 20
... Analog Dialogue article Wideband A/D information. In general, the precise values depend on the application. The analog inputs of the AD9228 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that V recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 44 to Figure 47 ...
Page 21
... Rev Page SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 46. SNR/SFDR vs. Common-Mode Voltage 2.4 MHz MSPS IN SAMPLE 90 85 SFDR (dBc SNR (dB 0.2 0.4 0.6 0.8 1.0 1.2 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 47. SNR/SFDR vs. Common-Mode Voltage MHz MSPS IN SAMPLE AD9228 1.4 1.6 1.4 1.6 ...
Page 22
... In the case of the AD9228, the largest input span available p-p. Differential Input Configurations There are several ways to drive the AD9228 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the ...
Page 23
... ADC 100Ω AD9228 the AD9228. When the DCS is on, noise and distortion perfor- 0.1µF CLK– mance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode ...
Page 24
... Figure 57. Ideal SNR vs. Input Frequency and Jitter Power Dissipation and Power-Down Mode As shown in Figure 58 and Figure 59, the power dissipated by ) the AD9228 is proportional to its sample rate. The digital power A dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS × ...
Page 25
... CH1 200mV/DIV = DCO CH2 200mV/DIV = DATA CH3 500mV/DIV = FCO Figure 60. AD9228-65, LVDS Output Timing Example in ANSI-644 Mode (Default) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 61 ...
Page 26
... AD9228 EYE: ALL BITS 500 0 –500 –1ns –0.5ns 0ns 100 50 0 –100ps 0ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only ULS: 9600/15600 EYE: ALL BITS 200 0 – ...
Page 27
... Data Sheet Two output clocks are provided to assist in capturing data from the AD9228. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9228 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) Table 9 ...
Page 28
... Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9228 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence Initial ...
Page 29
... Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9228 gained up internally by a factor of 2, setting V to 1.0 V, which results in a full-scale differential input span p-p. The V pin can be driven externally with a 1.0 V reference to improve ...
Page 30
... The analog input full- scale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. If the reference of the AD9228 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 66 depicts how the internal reference voltage is affected by loading ...
Page 31
... If multiple SDIO pins share a common connection, care should be taken to ensure that proper V same load for each AD9228, Figure 68 shows the number of SDIO pins that can be connected together and the resulting V level. This interface is flexible enough to be controlled by either ...
Page 32
... AD9228 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 NUMBER OF SDIO PINS CONNECTED TOGETHER Figure 68. SDIO Pin Loading CSB SCLK DON’T CARE R SDIO DON’ ...
Page 33
... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9228 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. ...
Page 34
... Bit 5 Bit 4 Bit 3 Bit 2 Soft 1 1 Soft reset reset off 0 = off (default) (default) 8-bit Chip ID Bits [7:0] (AD9228 = 0x02), (default Clock Clock Data Data Channel Channel Channel Channel DCO FCO ...
Page 35
... Rev Page AD9228 Default (LSB) Value Default Notes/ Bit 1 Bit 0 (Hex) Comments 00 = offset binary 0x00 Configures the (default) outputs and the 01 = twos format of the complement data ...
Page 36
... AD9228. An exposed continuous copper plane on the PCB should mate to the AD9228 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. ...
Page 37
... Figure 73 to Figure 77). Figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the AD9228 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter ...
Page 38
... AD9228 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9228 Rev. A evaluation board. POWER: Connect the switching power supply that is provided with the evaluation kit between a rated 100 240 V ac wall outlet and P503. ...
Page 39
... Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev Page AD9228 ...
Page 40
... AD9228 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 DNP AIN R102 64.9Ω VGA INPUT CONNECTION CHANNEL B P103 AIN P106 DNP VGA INPUT CONNECTION INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω AVDD_DUT VGA INPUT CONNECTION INH4 CHANNEL D P107 ...
Page 41
... CHB B – AVDD CHC AVDD CHC C – VIN CHD – VIN CHD D – Rev Page AD9228 GND RSET S10 32 7 VREF ...
Page 42
... AD9228 POPULATE L301-L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. 10kΩ R313 10kΩ DNP C311 0.1µF C312 0.1µF R315 C315 10kΩ 10µF DNP: DO NOT POPULATE Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit ...
Page 43
... J401 PICVCC 1 2 PICVCC GP1 3 4 GP1 GP0 5 6 GP0 MCLR/GP3 7 8 MCLR/GP3 9 10 PIC PROGRAMMING HEADER GAIN NEGATIVE SLOPE GAIN POSITIVE PIN MODE 0.018µF 274Ω C420 R416 8 AVDD_5V AVDD_5V 2 1 GAIN LO GAIN HI PIN HILO OPTIONAL AD9228 ...
Page 44
... AD9228 Figure 77. Evaluation Board Schematic, Power Supply Inputs Rev Page Data Sheet 05727-019 GND GND 1 1 GND GND 1 1 ...
Page 45
... Data Sheet Figure 78. Evaluation Board Layout, Primary Side Rev Page AD9228 ...
Page 46
... AD9228 Figure 79. Evaluation Board Layout, Ground Plane Rev Page Data Sheet ...
Page 47
... Data Sheet Figure 80. Evaluation Board Layout, Power Plane Rev Page AD9228 ...
Page 48
... AD9228 Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page Data Sheet ...
Page 49
... SOT- mA, dual Schottky LED 603 Green candela Diode DO-214AB SMC Diode DO-214AA SMC Rev Page AD9228 Manufacturer’s Manufacturer Part Number Murata GRM155R71C104KA88D Murata GRM1555C1H2R2GZ01B Murata GRM219R60J106KE19D Murata GRM188C70J225KE20D Murata GRM155R71H102KA01D AVX ...
Page 50
... AD9228 Item Qty. Reference Designator 17 1 F501 18 1 FER501 19 12 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 20 1 JP301 21 2 J205, J402 22 1 J201 to J204 23 1 J401 24 8 L501, L502, L503, L504, L505, L506, L507, L508 ...
Page 51
... W, 1% tol Switch SMD Light touch, 100GE Transformer CD542 ADT1-1WT, 1:1 impedance ratio transformer IC SOT-223 ADP33339AKC-1.8, 1.5 A, 1.8 V LDO regulator Rev Page AD9228 Manufacturer’s Manufacturer Part Number NIC NRC04F1001TRF Components NIC NRC04J330TRF Components NIC NRC04F4990TRF Components NRC04F1003TRF NIC Components NIC ...
Page 52
... RAM size 64 × MHz speed, PIC12F controller series Rev Page Data Sheet Manufacturer’s Manufacturer Part Number Analog Devices AD8332ACPZ Analog Devices ADP3339AKCZ-5 Analog Devices ADP3339AKCZ-3.3 Analog Devices AD9228BCPZ-65 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ Fairchild NC7WZ07P6X_NL Fairchild NC7WZ16P6X_NL Microchip PIC12F629-I/SN ...
Page 53
... Notes Temperature Range AD9228ABCPZ-40 −40°C to +85°C AD9228ABCPZRL7-40 −40°C to +85°C AD9228ABCPZ-65 −40°C to +85°C AD9228ABCPZRL7-65 −40°C to +85°C 3 AD9228-65EBZ RoHS Compliant Part. 2 Reference PCN 09_0156. 3 Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. 7.10 0.60 MAX 7.00 SQ 6.90 ...
Page 54
... AD9228 NOTES Rev Page Data Sheet ...
Page 55
... Data Sheet NOTES Rev Page AD9228 ...
Page 56
... AD9228 NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05727-0-12/11(E) Rev Page Data Sheet ...