AD7276 Analog Devices, AD7276 Datasheet
AD7276
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AD7276 Summary of contents
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... AD7476A pin-compatible GENERAL DESCRIPTION The AD7276/AD7277/AD7278 are 12-/10-/8-bit, high speed, low power, successive approximation analog-to-digital converters (ADCs), respectively. The parts operate from a single 2. 3.6 V power supply and feature throughput rates MSPS. The parts contain a low noise, wide bandwidth track- and-hold amplifier that can handle input frequencies in excess of 55 MHz ...
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... Features .............................................................................................. 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AD7276 Specifications................................................................. 3 AD7277 Specifications................................................................. 5 AD7278 Specifications................................................................. 7 Timing Specifications—AD7276/AD7277/AD7278 ............... 8 Timing Examples........................................................................ 10 Absolute Maximum Ratings.......................................................... 11 ESD Caution................................................................................ 11 Pin Configurations and Function Descriptions ......................... 12 Typical Performance Characteristics ........................................... 13 Terminology .................................................................................... 15 REVISION HISTORY 5/11—Rev Rev. C Changes to Figure 21 ...
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... SPECIFICATIONS AD7276 SPECIFICATIONS Grade and A Grade unless otherwise noted. MAX Table 2. Parameter DYNAMIC PERFORMANCE 4 Signal-to-Noise + Distortion (SINAD) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) 4 Peak Harmonic or Spurious Noise (SFDR) 4 Intermodulation Distortion (IMD) Second-Order Terms Third-Order Terms ...
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... AD7276/AD7277/AD7278 Parameter CONVERSION RATE Conversion Time 4 Track-and-Hold Acquisition Time Throughput Rate POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 6 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Y Grade specifications are guaranteed by characterization. ...
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... Straight (natural) binary 250 250 ns max min 3.45 3.45 MSPS max Rev Page AD7276/AD7277/AD7278 Test Conditions/Comments MHz sine wave MHz 0.97 MHz MHz 0.97 MHz @ 0.1 dB Guaranteed no missed codes to 10 bits −40°C to +85°C 85°C to 125°C When in track When in hold 2.35 V ≤ ...
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... AD7276/AD7277/AD7278 Parameter POWER REQUIREMENTS Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode (Static) Full Power-Down Mode (Static) 5 Power Dissipation Normal Mode (Operational) Partial Power-Down Full Power-Down 1 Temperature range from −40°C to +125°C. 2 Typical specifications are tested with and at 25° ...
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... V − 0 0.2 0.2 ±2.5 ±2.5 4.5 4.5 Straight (natural) binary 208 208 Rev Page AD7276/AD7277/AD7278 Unit Test Conditions/Comments MHz sine wave IN dB min dB max dB typ dB typ dB typ MHz 0.97 MHz dB typ MHz 0.97 MHz MHz typ @ 3 dB MHz typ @ 0.1 dB Bits ...
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... Temperature range from −40°C to +125°C. 2 Typical specifications are tested with and at 25° See the Terminology section. 4 Guaranteed by characterization. 5 See the Power vs. Throughput Rate section. TIMING SPECIFICATIONS—AD7276/AD7277/AD7278 MIN MAX Table 5. Parameter ...
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... SCLK SDATA Figure 2. Access Time After SCLK Falling Edge t 7 SCLK V IH SDATA V IL Figure 3. Hold Time After SCLK Falling Edge SCLK V IH SDATA V IL Figure 4. SCLK Falling Edge SDATA Three-State Rev Page AD7276/AD7277/AD7278 t 8 1.4V ...
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... AD7276/AD7277/AD7278 TIMING EXAMPLES For the AD7276 brought high during the 14 edge after the two leading zeros and 12 bits of the conversion have been provided, the part can achieve the fastest throughput rate, 3 MSPS brought high during the 16 edge after the two leading zeros and 12 bits of the conversion and two trailing zeros have been provided, a throughput rate of 2 ...
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... device reliability. −0 0 ±10 mA ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 230°C/W 92°C/W 205.9°C/W 43.74°C/W 255°C 260°C 1.5 kV Rev Page AD7276/AD7277/AD7278 ...
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... Data Out. Logic output. The conversion result from the AD7276/AD7277/AD7278 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7276 consists of two leading zeros followed by 12 bits of conversion data and two trailing zeros, provided MSB first. ...
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... A –20 –40 –60 –80 –100 –120 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 FREQUENCY (kHz) Figure 10. AD7276 Dynamic Performance at 3 MSPS, Input Tone = 1 MHz –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – ...
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... CODE Figure 17. AD7276 INL Performance = 10Ω 0Ω IN 1000 1500 3000 3500 4000 Rev Page 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 500 1000 1500 2000 2500 3000 CODE Figure 18. AD7276 DNL Performance 3500 4000 ...
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... TERMINOLOGY Integral Nonlinearity The maximum deviation from a straight line passing through the endpoints of the ADC transfer function. For the AD7276/ AD7277/AD7278, the endpoints of the transfer function are zero scale at 0.5 LSB below the first code transition and full scale at 0.5 LSB above the last code transition. ...
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... CONTROL with two leading zeros followed by the 12-bit, 10-bit, or 8-bit LOGIC result. The 12-bit result from the AD7276 is followed by two trailing zeros; the 10-bit and 8-bit results from the AD7277 and AD7278 are followed by four and six trailing zeros, respectively. Alternatively, because the supply current required by the AD7276/ AD7277/AD7278 is so low, a precision reference can be used as the supply source for the AD7276/AD7277/AD7278 ...
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... Instead, the digital inputs applied to the AD7276/AD7277/ AD7278 can and are not restricted by the V limit of the analog inputs. For example, if the AD7276/AD7277/ AD7278 are operated with used on the digital inputs. However important to note ...
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... SCLK falling edge, the part remains powered up, but the con- version is terminated and SDATA goes back into three-state. For the AD7276, a minimum of 14 serial clock cycles are required to complete the conversion and access the complete conversion result. For the AD7277 and AD7278, a minimum of 12 and 10 serial clock cycles are required to complete the conversion and to access the complete conversion result, respectively ...
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... To exit this mode of operation and power up the AD7276/ AD7277/AD7278, users should perform a dummy conversion. On the falling edge of , the device begins to power up and CS continues to power up as long as is held low until after the CS th falling edge of the 10 SCLK. The device is fully powered up once 16 SCLKs elapse ...
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... AD7276/AD7277/AD7278 THE PART BEGINS TO POWER SCLK A SDATA INVALID DATA THE PART ENTERS PARTIAL POWER-DOWN SCLK INVALID DATA SDATA THE PART BEGINS TO POWER SCLK SDATA INVALID DATA THE PART IS FULLY POWERED UP, SEE THE POWER- UP TIMES SECTION Figure 26. Exiting Partial Power-Down Mode ...
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... V). If the power-up time is one DD dummy cycle, that is, 333 ns, and the remaining conversion time is 290 ns, then the AD7276/AD7277/AD7278 can be said to dissipate 12.6 mW for 623 ns during each conversion cycle. If the throughput rate is 200 kSPS, then the cycle time is 5 μs and the average power dissipated during each cycle is 623/5,000 × ...
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... DB11 DB10 DB9 DB1 1/THROUGHPUT Figure 31. AD7276 Serial Interface Timing Diagram 14 SCLK Cycle Rev Page SCLK falling edge, as shown in Figure 34. SCLK falling edge. Then the last two trailing zeros are th rising SCLK edge ...
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... CS t CONVERT SCLK t 3 SDATA Z ZERO DB11 DB10 THREE- STATE 2 LEADING ZEROS Figure 32. AD7276 Serial Interface Timing Diagram 16 SCLK Cycle CS t CONVERT SCLK SDATA Z ZERO DB9 DB8 THREE- STATE 2 LEADING ZEROS Figure 33. AD7277 Serial Interface Timing Diagram ...
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... This allows a value for t , satisfying the minimum QUIET requirement of 4 ns. MICROPROCESSOR INTERFACING AD7276/AD7277/AD7278-to-ADSP-BF53x The ADSP-BF53x family of DSPs interfaces directly to the AD7276/AD7277/AD7278 without requiring glue logic. The SPORT0 Receive Configuration 1 Register should be set up as outlined in Table 9. AD7276/ ADSP-BF53x* AD7277/ SPORT0 ...
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... This design facilitates using ground planes that can easily be separated. To provide optimum shielding for ground planes, a minimum etch technique is generally best. All AGND pins of the AD7276/ AD7277/AD7278 should be sunk into the AGND plane. Digital and analog ground planes should be joined in one place only. If ...
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... AD7276/AD7277/AD7278 OUTLINE DIMENSIONS 1.60 BSC PIN 1 INDICATOR * 0.90 0.87 0.84 0.10 MAX 3.20 3.00 2.80 IDENTIFIER 0.95 0.85 0.75 COPLANARITY 2.90 BSC 2.80 BSC 0.95 BSC 1.90 BSC 0.20 * 1.00 MAX 0.08 8° SEATING 0.50 PLANE 4° 0.30 0° * COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. Figure 37. 6-Lead Thin Small Outline Transistor Package [TSOT] (UJ-6) Dimensions shown in millimeters 3 ...
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... This board is a complete unit allowing control and communicate with all Analog Devices evaluation boards that end designator. To order a complete evaluation kit, the particular ADC evaluation board (such as EVAL-AD7276CBZ), the EVAL-CONTROL BRD2, and transformer must be ordered. See the relevant evaluation board user guide for more information ...
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... AD7276/AD7277/AD7278 NOTES ©2005–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04903-0-5/11(C) Rev Page ...