AD7623 Analog Devices, AD7623 Datasheet
AD7623
Specifications of AD7623
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AD7623 Summary of contents
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... Instrumentation Spectrum analysis ATE GENERAL DESCRIPTION The AD7623 is a 16-bit, 1.33 MSPS, charge redistribution SAR, fully differential analog-to-digital converter (ADC) that operates from a single 2.5 V power supply. It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports ...
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... Driver Amplifier Choice ........................................................... 17 Voltage Reference Input ............................................................ 18 Power Supply............................................................................... 19 Power Dissipation vs. Throughput .......................................... 20 Conversion Control ................................................................... 20 Interfaces.......................................................................................... 21 Digital Interface.......................................................................... 21 Parallel Interface......................................................................... 21 Serial Interface ............................................................................ 22 Master Serial Interface............................................................... 22 Slave Serial Interface .................................................................. 24 Microprocessor Interfacing....................................................... 26 Application ...................................................................................... 27 Layout .......................................................................................... 27 Evaluating the AD7623 Performance ...................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 Rev Page ...
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... AD7623 Unit Bits μA ns MSPS 4 LSB Bits LSB LSB LSB LSB ppm/° FSR ppm/°C LSB MHz ns ...
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... AD7623 Parameter EXTERNAL REFERENCE Voltage Range Current Drain REFERENCE BUFFER REFBUFIN Input Voltage Range TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels DIGITAL OUTPUTS Data Format 7 8 Pipeline Delay POWER SUPPLIES ...
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... L Rev Page AD7623 , unless otherwise noted. MAX Min Typ Max 750 23 560 1 10 560 125 15 10 600 560 ...
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... AD7623 SERIAL CLOCK TIMING SPECIFICATIONS Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. = 91°C/ 26°C/W. JA Rev Page AD7623 ...
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... When SER/ PAR = low, this output is used as Bit 6 of the parallel port data output bus. or INVSCLK Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal AGND 1 PIN 1 AVDD IDENTIFIER BYTESWAP 4 OB/2C 5 AD7623 DGND 6 TOP VIEW DGND 7 (Not to Scale) SER/PAR D2/DIVSCLK[0] 11 D3/DIVSCLK[1] 12 ...
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... RESET DI Reset Input. When high, reset the AD7623. Current conversion if any is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If not used, this pin can be tied to DGND. 34 ...
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... AD7623 1 Pin No. Mnemonic Type Description 35 CNVST DI Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. 36 AGND P Analog Power Ground Pin. 37 REF AI/O Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 2.048 V on this pin. ...
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... CNVST input to when the input signal is held for a conversion. Transient Response The time required for the AD7623 to achieve its rated accuracy after a full-scale step function is applied to its input. Reference Voltage Temperature Coefficient Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25° ...
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... AD7623 TYPICAL PERFORMANCE CHARACTERISTICS 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 16384 32768 CODE Figure 5. Integral Nonlinearity vs. Code 160k 147157 140k 120k 100k 80k 58814 60k 50472 40k 20k 2406 7FFC 7FFD 7FFE 7FFF 8000 8001 CODE IN HEX Figure 6. Histogram of 261,120 Conversions Input at the Code Center (External 2 ...
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... Figure 14. FFT 100 kHz SNR SINAD ENOB –35 – 105 TEMPERATURE (°C) Figure 15. SNR, SINAD, and ENOB vs. Temperature SFDR THD THIRD HARMONIC SECOND HARMONIC –35 – 105 TEMPERATURE (°C) AD7623 600 15.5 15.0 14.5 14.0 13.5 125 100 125 ...
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... AD7623 91.0 90.5 SNR SINAD 90.0 89.5 89.0 –60 –50 –40 –30 INPUT LEVEL (dB) Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale AVDD –55 –35 – TEMPERATURE (°C) Figure 18. Power-Down Operating Currents vs. Temperature 100k 10k 100 0.1 –20 –10 0 280 ...
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... ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7623 can be operated from a single 2.5 V supply and be interfaced to either 2.5 V digital logic housed in 48-lead LQFP or tiny LFCSP packages that combine space savings with flexibility, allowing the AD7623 to be configured as either a serial or parallel interface ...
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... AD7623 TRANSFER FUNCTIONS Using the OB/ 2C digital input, the AD7623 offers two output codings: straight binary and twos complement. The LSB size with V = 2.048 × V /65536, which is 62.5 μV. Refer to REF REF Figure 22 and Table 7 for the ideal transfer characteristic. 111...111 111 ...
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... Figure 26. THD vs. Analog Input Frequency and Source Resistance DRIVER AMPLIFIER CHOICE Although the AD7623 is easy to drive, the driver amplifier must meet the following requirements: • Together, the driver amplifier and the AD7623 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0 ...
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... RC filter in Figure 23, and without using it. • The driver needs to have a THD performance suitable to that of the AD7623. Figure 13 gives the THD vs. frequency that the driver should exceed. The AD8021 meets these requirements and is appropriate for almost all applications. The AD8021 needs external compensation capacitor that should have good linearity as an NPO ceramic or mica type ...
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... AD8021 Figure 28. Use of the Temperature Sensor POWER SUPPLY The AD7623 uses three sets of power supply pins: an analog 2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a digital input/output interface supply OVDD. The OVDD supply allows direct interface with any logic working between 2.3 V and 5 ...
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... SAMPLING RATE (SPS) Figure 30. Power Dissipation vs. Sample Rate CONVERSION CONTROL The AD7623 is controlled by the CNVST input. A falling edge on CNVST is all that is necessary to initiate a conversion. Detailed timing diagrams of the conversion process are shown in Figure 31. Once initiated, it cannot be restarted or aborted, even by the power-down input, PD, until the conversion is complete ...
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... RD is generally used to enable the conversion result on the data bus. RESET The RESET input is used to reset the AD7623 and generate a fast initialization. A rising edge on RESET aborts the current conversion (if any) and tristates the data bus. The falling edge of RESET clears the data bus and engages the initialization process indicated by pulsing BUSY high ...
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... Figure 36. 8-Bit and 16-Bit Parallel Interface SERIAL INTERFACE The AD7623 is configured to use the serial interface when SER/ PAR is held high. The AD7623 outputs 16 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 16 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock ...
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... Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert) RDC/SDIN = 0 INVSCLK = INVSYNC = D14 RDC/SDIN = 1 INVSCLK = INVSYNC = Rev Page AD7623 ...
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... Figure 40 and Figure 41 show the detailed timing diagrams of these methods. While the AD7623 is performing a bit decision important that voltage transients be avoided on digital input/output pins, or degradation of the conversion result could occur. This is ...
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... SDOUT X D15 D14 t 16 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert INVSCLK = D13 D1 D0 X13 INVSCLK = D13 D2 D0 Rev Page AD7623 18 X15 X14 Y15 Y14 ...
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... Figure 42 shows an interface diagram between the AD7623 and an SPI-equipped DSP, ADSP-219x. To accommodate the slower speed of the DSP, the AD7623 acts as a slave device, and data must be read after conversion. This mode also allows the daisy- chain feature. The convert command could be initiated in response to an internal timer interrupt ...
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... Digital and analog ground planes should be joined in only one place, preferably underneath the AD7623 close as possible to the AD7623. If the AD7623 system where multiple devices require analog-to-digital ground connections, the connections should still be made at one point only, a star ground point, established as close as possible to the AD7623 ...
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... AD7623ACPRL −40°C to +85°C 1 AD7623ACPZ −40°C to +85°C 1 AD7623ACPZRL −40°C to +85°C AD7623AST −40°C to +85°C AD7623ASTRL −40°C to +85°C 1 AD7623ASTZ −40°C to +85°C 1 AD7623ASTZRL −40°C to +85°C 2 EVAL-AD7623CB 3 EVAL-CONTROL BRD3 Pb-free part ...