AD7745 Analog Devices, AD7745 Datasheet - Page 14

• Manufacturer Part Number: AD7745
• Description: 24-bit, 1 Channel Capacitance to Digital Converter
• Manufacturer: Analog Devices

Specifications of AD7745

• Resolution (bits): 24bit
• # Chan: 1
• Sample Rate: n/a
• Interface: I²C/Ser 2-Wire,Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,± 4 pF (Delta C)
• Adc Architecture: Sigma-Delta
• Pkg Type: SOP

AD7745/AD7746
REGISTER DESCRIPTIONS
The master can write to or read from all of the AD7745/
AD7746 registers except the address pointer register, which is a
write-only register. The address pointer register determines
which register the next read or write operation accesses. All
communications with the part through the bus start with an
access to the address pointer register. After the part has been
Table 8. Register Summary
Register
Status
Cap Data H
Cap Data M
Cap Data L
VT Data H
VT Data M
VT Data L
Cap Setup
VT Setup
EXC Setup
Configuration
Cap DAC A
Cap DAC B
Cap Offset H
Cap Offset L
Cap Gain H
Cap Gain L
Volt Gain H
Volt Gain L
1
The CIN2 bit is relevant only for AD7746. The CIN2 bit should always be 0 on the AD7745.
(Dec) (Hex)
10
11
12
13
14
15
16
17
18
Address
0
1
2
3
4
5
6
7
8
9
Pointer
0x0A
0x0D
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0B
0x0C
0x0E
0x0F
0x10
0x11
0x12
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
R
R
R
R
R
R
R
DACAENA
DACBENB
CLKCTRL
CAPEN
VTFS1
VTEN
Bit 7
0
0
0
0
1
0
0
-
VTMD1
EXCON
VTFS0
CIN2
Bit 6
0
0
0
0
0
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-
Capacitive gain calibration—high byte, factory calibrated
1
Capacitive gain calibration—low byte, factory calibrated
Voltage/temperature channel data—middle byte, 0x00
Voltage gain calibration—high byte, factory calibrated
Voltage gain calibration—low byte, factory calibrated
Voltage/temperature channel data—high byte, 0x00
Voltage/temperature channel data—low byte, 0x00
Capacitive offset calibration—high byte, 0x80
CAPDIFF
Capacitive offset calibration—low byte, 0x00
CAPFS2
Capacitive channel data—middle byte, 0x00
VTMD0
EXCB
Bit 5
Capacitive channel data—high byte, 0x00
Capacitive channel data—low byte, 0x00
0
0
0
0
1
-
accessed over the bus and a read/write operation is selected, the
address pointer register is set up. The address pointer register
determines from or to which register the operation takes place.
A read/write operation is performed from/to the target address,
which then increments to the next address until a stop
command on the bus is performed.
CAPFS1
EXTREF
EXCB
Bit 4
Default Value
0
0
0
0
0
-
-
DACA—7-Bit Value
DACB—7-Bit Value
EXCERR
CAPFS0
EXCA
Bit 3
0x00
0x00
0
0
0
0
0
-
-
EXCA
Bit 2
MD2
RDY
1
0
0
0
0
-
-
VTSHORT
EXCLVL1
RDYVT
Bit 1
MD1
1
0
0
1
0
-
CAPCHOP
EXCLVL0
RDYCAP
VTCHOP
Bit 0
MD0
1
0
0
1
0