AD9229 Analog Devices, AD9229 Datasheet
AD9229
Specifications of AD9229
Related parts for AD9229
AD9229 Summary of contents
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... MHz and supports double-data rate operation (DDR). 3. The outputs of each ADC are serialized LVDS with data rates up to 780 Mbps (12 bits × 65 MSPS). 4. The AD9229 operates from a single 3.0 V power supply. 5. Packaged in a Pb-free, 48-lead LFCSP package. 6. The internal clock duty cycle stabilizer maintains performance over a wide range of input clock duty cycles ...
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... AD9229 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagram ............................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 REVISION HISTORY 5/10—Rev Rev. B Change to Item 47 in Table 11 ...................................................... 38 Updated Outline Dimensions ...
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... Full IV 2.7 3.0 Full IV 2.7 3.0 Full VI 300 Full VI 28 Full VI 985 Full V 3 Full V –95 Rev Page AD9229 AD9229-65 Max Min Typ Max 12 Guaranteed ±25 ±5 ±25 ±25 ±5 ±25 ±2.5 ±0.3 ±2.5 ±1.5 ±0.2 ±1.5 ±0.3 ±0.6 ±0.3 ±0.7 ±0.4 ±1 ±0.4 ± ...
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... Full V 25°C V Full VI Full VI 25°C V Full V 25°C V Full VI Full VI 25°C V Full V 25°C V Full VI Full VI 25° MHz 25° MHz = 69 MHz 25° MHz Rev Page AD9229-50 AD9229-65 Min Typ Max Min Typ 69.5 70.4 69.0 70.2 70.4 70.2 68.7 69.6 68.0 69.5 67.2 67.1 70.0 69.8 70.0 69.8 68.4 69.4 67.3 69.0 66.8 66.7 11.3 11.3 11.3 11.3 11.1 11.2 10.9 11.2 10.8 10 ...
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... TTL/CMOS IV 2.0 IV 0.8 VI 0.5 ±10 VI 0.5 ± 2.0 IV 0.8 IV 0.5 ±10 IV 0.5 ± LVDS VI 260 440 VI 1.15 1.25 1.35 VI Offset binary Rev Page AD9229 AD9229-65 Min Typ Max Unit TTL/CMOS 2.0 V 0.8 V 0.5 ±10 μA 0.5 ±10 μ 2.0 V 0.8 V 0.5 ±10 μA 0.5 ±10 μ LVDS 260 440 mV 1.15 1.25 1.35 V Offset ...
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... SAMPLE SAMPLE SAMPLE 250 250 (t /24) – (t /24) (t /24) + SAMPLE SAMPLE SAMPLE 250 250 ±100 ±250 4 10 1.8 <1 2 Rev Page AD9229-65 Min Typ Max 65 10 6.2 7.7 6.2 7.7 3.3 6.5 7.9 250 250 6 FCO (t /24) SAMPLE (t /24) – (t /24) (t /24) + SAMPLE SAMPLE SAMPLE ...
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... – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) Figure 2. Timing Diagram Rev Page MSB D10 (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – – 9) AD9229 ...
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... AD9229 ABSOLUTE MAXIMUM RATINGS Table 5. With Parameter Respect To ELECTRICAL AVDD AGND DRVDD DRGND AGND DRGND AVDD DRVDD Digital Outputs (D+, D–, DRGND DCO+, DCO–, FCO+, FCO–) LVDSBIAS DRGND CLK AGND VIN+, VIN– AGND PDWN, DTP AGND REFT, REFB ...
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... TOP VIEW (Not to Scale Figure 3. LFCSP Top View Pin No Rev Page AD9229 36 DRGND 35 DRVDD 34 LVDSBIAS 33 AGND 32 AVDD 31 AGND 30 CLK 29 AVDD 28 AGND 27 VIN+D 26 VIN–D 25 AGND Mnemonic Description VIN–D ADC D Analog Input— ...
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... AD9229 EQUIVALENT CIRCUITS AVDD VIN+, VIN– AGND Figure 4. Equivalent Analog Input Circuit AVDD CLK 170Ω AGND Figure 5. Equivalent Clock Input Circuit AVDD PDWN 375Ω AGND Figure 6. Equivalent Digital Input Circuit V D– V Figure 7. Equivalent Digital Output Circuit DTP Figure 8 ...
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... SFDR (dBc p-p, SNR (dB p-p, SNR (dB ENCODE (MSPS) Figure 14. SNR/SFDR vs MHz, f SAMPLE IN AD9229 AIN = –0.5dBFS SNR = 68.1dB ENOB = 11.0 BITS SFDR = 77.0dBC 24.4 28.4 32 MSPS SAMPLE AIN = –0.5dBFS MSPS SAMPLE AIN = –0.5dBFS 40 45 ...
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... AD9229 95 1V p-p, SFDR (dBc p-p, SFDR (dBc p-p, SNR (dB p-p, SNR (dB ENCODE (MSPS) Figure 15. SNR/SFDR vs 10.3 MHz, f SAMPLE p-p, SFDR (dBc p-p, SFDR (dBc p-p, SNR (dB p-p, SNR (dB ENCODE (MSPS) Figure 16. SNR/SFDR vs. f ...
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... Figure 25. Two-Tone SFDR vs. Analog Input Level, f IN2 24.4 28.4 32.5 – MHz, Figure 26. SINAD/SFDR vs. Temperature, f IN2 Rev Page AD9229 2V p-p, SFDR (dBc REFERENCE 1V p-p, SFDR (dBc) –56 –52 –48 –44 –40 –36 –32 –28 –23 –19 –15 ANALOG INPUT LEVEL (dBFS MHz and ...
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... AD9229 –5 –10 –15 –20 –40 – TEMPERATURE (°C) Figure 27. Gain Error vs. Temperature 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 512 1024 1536 2048 CODE Figure 28. Typical INL 2.4 MHz 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0.5 0 512 1024 1536 2048 CODE Figure 29 ...
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... FREQUENCY (MHz) Figure 33. Full Power Bandwidth vs. Frequency, f 400 450 500 = 65 MSPS SAMPLE Rev Page AD9229 ...
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... AD9229 TERMINOLOGY Analog Bandwidth Analog bandwidth is the analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced from full scale. Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the 50% point rising edge of the clock input to the time at which the input signal is held for conversion ...
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... The peak spurious component may or may not be an IMD product. It may be reported in decibels relative to the carrier (that is, degrades as signal levels are lowered decibels relative to full scale (always related back to converter full scale). Rev Page AD9229 ...
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... This passive network creates a low-pass filter at the ADC’s input; therefore, the precise values are dependent on the application. The analog inputs of the AD9229 are not internally dc-biased. In ac-coupled applications, the user must provide this bias externally. For optimum performance, set the device so that V = AVDD/2 ...
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... Figure 37. Differential Input Configuration Using the AD8332 However, the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9229. For applications where SNR is a key parameter, differential transfor- mer coupling is the recommended input configuration. An example of this is shown in Figure 38. ...
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... Figure 41. Supply Current vs asserting the PDWN pin high, the AD9229 is placed in power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed in a high impedance state. Reasserting the PDWN pin low returns the AD9229 to normal operating mode ...
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... MSPS = 780 bps). The lowest typical conversion rate is 10 MSPS. Two output clocks are provided to assist in capturing data from the AD9229. The DCO is used to clock the output data and is equal to six times the sampling clock (CLK) rate. Data is clocked out of the AD9229 and can be captured on the rising and falling edges of the DCO that supports double-data rate (DDR) capturing ...
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... SELECT R2 LOGIC SENSE R1 Figure 43. Programmable Reference Configuration If the internal reference of the AD9229 is used to drive multiple converters to improve gain matching, the loading of the refer- ence by the other converters must be considered. Figure 44 depicts how the internal reference voltage is affected by loading. 0.05 0 –0.05 –0.10 – ...
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... AD9229. A continuous exposed copper plane on the PCB should mate to the AD9229 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. ...
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... Figure 48 to Figure 52). Figure 47 shows the typical bench characterization setup used to evaluate the ac performance of the AD9229 critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the ultimate performance of the converter ...
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... DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings or modes allowed on the AD9229 Rev C evaluation board. • POWER: Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V to 240 V ac wall outlet and P503. ...
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... AD9229 VGA INPUT CONNECTION INH1 CHANNEL A R101 P101 0Ω DNP A IN R102 65Ω VGA INPUT CONNECTION INH2 CHANNEL B R114 P103 0Ω DNP A IN R115 65Ω VGA INPUT CONNECTION INH3 CHANNEL C R127 P105 0Ω DNP A IN R128 65Ω VGA INPUT CONNECTION INH4 ...
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... R222 0Ω AVDD_DUT VREF = EXTERNAL R219 DNP C208 R223 10μF 0Ω VREF = 0. R219/R220) R224 R220 0Ω DNP VREF = 1V REMOVE C208 WHEN USING EXTERNAL VREF Rev Page AD9229 36 DRGND GND 35 DRVDD DRVDD_DUT 34 LVDSBIAS 33 AGND GND R204 4.0kΩ 32 AVDD AVDD_DUT 31 AGND GND ...
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... AD9229 POPULATE L305 TO L312 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER AVDD_VGA R312 10Ω R311 10kΩ DNP C313 0.1μF C315 0.1μF R314 C317 10kΩ 10μF 0.1μF DNP : DO NOT POPULATE Figure 50. Evaluation Board Schematic, Optional DUT Analog Input Drive CH_D ...
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... C421 C422 0.1μF 0.1μF C425 C426 22pF 22pF L413 L414 120nH C427 C428 0.1μF 0.1μF INH2 INH1 Rev Page AD9229 C412 R409 0.1μF 100kΩ DNP AVDD_VGA R409 10kΩ VG DNP C414 0.1μF C416 0.1μF C419 C420 R414 0.1μF 10μ ...
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... AD9229 POWER SUPPLY INPUT 6V 2A MAX U501 ADP33339AKC-3 3 PWR_IN INPUT OUTPUT1 C502 OUTPUT4 1μF GND 1 U503 ADP33339AKC-3 3 PWR_IN INPUT OUTPUT1 C506 OUTPUT4 1μF GND 1 DNP : DO NOT POPULATE F501 P503 SMDC110F 1 C501 10μ L504 10μH 2 DUT_AVDD 4 C503 1μF U502 ADP33339AKC-5 3 PWR_IN ...
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... CONNECTED TO GROUND DNP : DO NOT POPULATE Figure 53. Evaluation Board Schematic, Decoupling and Miscellaneous Rev Page C625 C628 0.1μF 0.1μF C632 0.1μF UNUSED GATES U202 5 6 GND AVDD_DUT : 14 GND : 7 U202 9 8 AVDD_DUT : 14 GND : 7 U202 11 10 AVDD_DUT : 14 GND : 7 U202 13 12 AVDD_DUT : 14 GND : 7 AD9229 ...
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... AD9229 Figure 54. Evaluation Board Layout, Primary Side Rev Page ...
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... Figure 55. Evaluation Board Layout, Ground Plane Rev Page AD9229 ...
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... AD9229 Figure 56. Evaluation Board Layout, Power Plane Rev Page ...
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... Figure 57. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev Page AD9229 ...
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... AD9229 Table 11. Evaluation Board Bill of Materials (BOM) Qnty. per Item Board REFDES 1 1 AD9229LFCSP_REVC 2 59 C327, C328, C630, C628, C629, C631, C632, C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C207, C313, C314, C315, ...
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... W Resistor 402 470 kΩ, 1/ tol Resistor 402 39 kΩ, 1/ tol Resistor 402 187 Ω, 1/ tol Rev Page AD9229 Mfg. Mfg. Part Number Panasonic - EXC-CL3225U1 ECG Murata LQG15HNR12J02B Panasonic ERJ-6GEY0R00V CTS REEVES CB3LV-3C-66M6666-T Johnson 142-0711-821 Components ...
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... IC SOT-223 ADP33339AKC-3, 1.5 A, 3.0 V LDO regulator IC LFCSP, CP- AD8332ACP, 32 ultralow noise precision dual VGA IC SOT-223 ADP33339AKC-5 IC LFCSP, CP- AD9229-65, quad 48-1 12-bit, 65 MSPS serial LVDS 3 V ADC IC SOT-23 ADR510AR, 1.0 V, precision low noise shunt voltage reference IC TSSOP 74VHC04MTC, hex inverter Part of CBSB-14-01A-RT, assembly 7/8" height, ...
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... LFCSP_VQ 48-Lead LFCSP_VQ 48-Lead LFCSP_VQ Rev Page 0.30 0.23 0.18 PIN 1 INDICATOR 5.55 EXPOSED 5.50 SQ PAD 5.45 (BOTTOM VIEW 0.22 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Package Option CP-48-8 CP-48-8 CP-48-8 CP-48-8 AD9229 ...
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... AD9229 NOTES © 2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04418–0–5/10(B) Rev Page ...