AD7933 Analog Devices, AD7933 Datasheet - Page 25

• Manufacturer Part Number: AD7933
• Description: 4-Channel, 1.5 MSPS, 10-Bit Parallel ADC with a Sequencer
• Manufacturer: Analog Devices

Specifications of AD7933

• Resolution (bits): 10bit
• # Chan: 4
• Sample Rate: 1.5MSPS
• Interface: Byte,Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: (2Vref) p-p,5V p-p,Uni (Vref),Uni (Vref) x 2,Uni 2.5V,Uni 5.0V
• Adc Architecture: SAR
• Pkg Type: SOP

Writing Data to the AD7933/AD7934
With W/ B tied logic high, a single write operation transfers the
full data-word on DB0 to DB11 to the control register on the
AD7933/AD7934. The DB8/HBEN pin assumes its DB8
function. Data written to the AD7933/AD7934 should be
provided on the DB0 to DB11 inputs, with DB0 being the LSB
of the data-word. With W/ B tied logic low, the AD7933/AD7934
requires two write operations to transfer a full 12-bit word.
DB8/HBEN assumes its HBEN function. Data written to the
AD7933/AD7934 should be provided on the DB0 to DB7
inputs. HBEN determines whether the byte written is high byte
or low byte data. The low byte of the data-word has DB0 being
the LSB of the full data-word. For the high byte write, HBEN
should be high and the data on the DB0 input should be Data
Bit 8 of the 12-bit word.
Figure 36. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Word Mode Operation (W/ B = 1)
Figure 37. AD7933/AD7934 Parallel Interface—Write Cycle Timing for Byte Mode Operation (W/ B = 0)
DB0 TO DB7
HBEN/DB8
WR
CS
DB0 TO DB11
WR
CS
t
18
t
4
t
LOW BYTE
4
t
6
Rev. B | Page 25 of 32
t
7
t
5
t
19
t
6
t
DATA
t
8
7
Figure 36 shows the write cycle timing diagram of the
AD7933/AD7934 in word mode. When operating in word
mode, the HBEN input does not exist and only one write
operation is required to write the word of data to the device.
Provide data on DB0 to DB11. When operating in byte mode,
the two write cycles shown in Figure 37 are required to write the
full data-word to the AD7933/AD7934. In Figure 37, the first
write transfers the lower eight bits of the data-word from DB0
to DB7, and the second write transfers the upper four bits of the
data-word.
When writing to the AD7933/AD7934, the top four bits in the
high byte must be 0s.
The data is latched into the device on the rising edge of WR .
The data needs to be set up a time, t
edge and held for a time, t
and WR signals are gated internally. CS and WR can be tied
together as the timing specifications for t
minimum (assuming CS and RD have not already been tied
together).
t
17
t
8
t
t
5
18
HIGH BYTE
8
, after the WR rising edge. The CS
t
19
7
, before the WR rising
AD7933/AD7934
4
and t
5
are 0 ns