AD9248 Analog Devices, AD9248 Datasheet - Page 7

• Manufacturer Part Number: AD9248
• Description: Dual 14-Bit, 20/40/65 MSPS, 3 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9248

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 65MSPS
• Interface: Par
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1 V p-p,2 V p-p,Uni 1.0V,Uni 2.0V
• Adc Architecture: Pipelined
• Pkg Type: QFP

SWITCHING SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
T
Table 4.
Parameter
SWITCHING PERFORMANCE
DATA OUTPUT PARAMETER
OUT-OF-RANGE RECOVERY TIME
1
2
3
The AD9248-65 model has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see Figure 24).
Output delay is measured from clock 50% transition to data 50% transition, with a 5 pF load on each output.
Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 μF and 10 μF capacitors on REFT and REFB.
MIN
Maximum Conversion Rate
Minimum Conversion Rate
CLK Period
CLK Pulse-Width High
CLK Pulse-Width Low
Output Delay
Pipeline Delay (Latency)
Aperture Delay (t
Aperture Uncertainty (t
Wake-Up Time
to T
ANALOG
CLOCK
MAX
INPUT
DATA
OUT
, DCS enabled, unless otherwise noted.
2
3
(t
PD
A
)
)
1
N–9
1
J
N–1
)
N–8
N
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
N–7
N+1
Test
Level
VI
V
V
V
V
VI
V
V
V
V
V
N–6
Min
50.0
15.0
15.0
2
20
N+2
AD9248BST/BCP-20
Figure 2. Timing Diagram
Rev. B | Page 7 of 48
N–5
Typ
3.5
7
1.0
0.5
2.5
2
N+3
Max
6
1
N–4
IN
N+4
= −0.5 dBFS differential input, 1.0 V internal reference,
Min
25.0
8.8
8.8
2
40
AD9248BST/BCP-40
N–3
N+5
Typ
3.5
7
1.0
0.5
2.5
2
N–2
N+6
Max
6
1
N–1
N+7
Min
65
15.4
6.2
6.2
2
AD9248BST/BCP-65
N
t
Typ
3.5
7
1.0
0.5
2.5
2
PD
N+8
=
MIN 2.0ns,
MAX 6.0ns
Max
1
6
AD9248
Unit
MSPS
MSPS
ns
ns
ns
ns
Cycles
ns
ps rms
ms
Cycles